設計與實現十進制浮點數運算硬體加速器於Nios II平台

Design and Implementation of Decimal Floating Point Hardware Accelerators on Nios II Platform

張恆偉(Heng-Wei Chang)

指導教授 ： 鄭福炯

大同大學/電機資訊學院/資訊工程學系所/碩士(2011年)

摘要

浮點數運算的算術運算是許多應用程式是不可或缺的一部分。許多商業和金融的應用程式所儲存的數值有一半以上為十進制數值，近年逐漸興起對十進制浮點數運算(Decimal floating point)的研究。使用軟體中十進制浮點數運算之函式庫如Java的BigDecimal或C#的Decimal可以滿足此類需求，但performance也會因此受限。
許多商用處理器已加入了Decimal Floating Point的運算功能，而Nios II 是一個在FPGA上廣泛使用的處理器，已經有很多各式各樣的BFP解決方案可以滿足浮點數運算的需求，但相對來說對於十進制運算需求的解決方案真的實屬少見。
本論文提出十進制浮點數運算的軟體演算法與硬體加速器實現方式，實做在Nios II處理器架構上增加了的Decimal Floating Point運算功能，包括客製化指令、硬體周邊、software function及嘗試使用C2H自動轉成hardware component。實驗數據顯示，使用C2H加速十進制運算功能比軟體快37 ~ 47倍、使用Custom Peripheral比軟體快96 ~ 447倍、作為客製化指令比軟體快 976 ~ 4542倍。

關鍵字

硬體加速器 ； 十進制浮點數

並列摘要

Floating Point Units are a vital part of digital systems. Recently, there is increasing interest in decimal floating-point arithmetic research due to many commercial and financial-based applications which require Decimal Floating Point arithmetic. The problem of using binary floating-point arithmetic in commercial and financial calculations is that most decimal floating-point numbers cannot be represented exactly in binary floating-point formats, and thus unacceptable errors may occur in the course of the computations. Therefore, these applications usually use software library instead, such as Java’s BigDecimal and C#’s Decimal, suffering from performance penalty.
Hardware decimal arithmetic units now are becoming an integral part of recently commercialized general purpose processors. This thesis designs and implements both software algorithms and hardware acceleration of Decimal Floating Point Arithmetic for Nios II platform. The experimental results show that C2H hardware accelerator, Custom Peripheral and Custom Instruction are 37 to 47, 96 to 447 and 976 to 4542 times faster than software functions, respectively.

並列關鍵字

Decimal Floating Point ； Hardware Accelerator ； Nios II

參考文獻

[l] M. F. Cowlishaw, "Decimal Floating-Point: Algorism for Computers", Proceedings of the 16th IEEE Symposium on Computer Anithmetic, Page 104-111, June 2003.

[4] IEEE, IEEE 754-2008 Standard for Floating-Point Arithmetic, 2008.

[10] Altera Corp. “Avalon Interface Specification”, Nov 2011.

[11] Altera Corp. “Avalon-MM Interface Specification”, Aug 2010.

[13] M. F. Cowlishaw, “Densely Packed Decimal Encoding,” IEEE Proceedings – Computers and Digital Techniques, vol. 149, May 2002, Page 102-104.