高吞吐率影像編碼轉換架構於高效能視訊編碼標準應用

本篇論文提出了High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT)的硬體架構，可支援4K(3840x2160)@30fps 的畫質，並且能夠針對不同尺寸的轉換單元(Transform Unit)32×32、16×16、8×8、4×4進行運算。使用一顆1-D IDCT Core以及一顆Transpose Memory來實現2-D的IDCT運算，在1-D IDCT Core裡採用16條運算路徑來實現高吞吐率，並且可以讓1-D和2-D的資料同時進行IDCT運算。在矩陣運算方面採用分散式演算法(Distributed Arithmetic)、加法器以及移位器，來取代傳統使用乘法器的矩陣運算。在製程技術上，使用台積電90 nm製程的製程技術來做合成，在2-D的轉換核心運算上有2G pels/s的吞吐率，整個架構的Gate counts為337K，硬體效率為5.93((〖10〗^3 pels)/s/gate)。

關鍵字

高效能視訊編碼；反離散餘閒轉換

並列摘要

In this paper, a hardware design which can support for High Efficiency Video Coding (HEVC) Inverse Discrete Cosine Transform (IDCT) for 32×32 Transform Unit (TU) sizes is proposed and is implemented by a using single 1-D IDCT core with a transpose memory to achieve low cost design. The proposed 1-D IDCT core employs 16 calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform core which can calculate 1st-D and 2nd-D data simultaneously in 32 parallel paths. The proposed 2-D transform core has a throughput rate of 2-Gpels/s with 337k gate counts when implemented into the TSMC 90nm CMOS technology.

並列關鍵字

IDCT ； HEVC ； integer IDCT ； video transform

參考文獻

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高吞吐率影像編碼轉換架構於高效能視訊編碼標準應用

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