混合式記憶體架構中適應性分頁與緩衝區機制之研究

Adaptive Page Allocation and Buffer Management of DRAM-PCM Hybrid Memory Architecture

鄭比傑(Pi-Chieh Cheng)

指導教授 ： 鄭維凱

中原大學/電機資訊學院/資訊工程研究所/碩士(2015年)

https://doi.org/10.6840/cycu201500737

摘要

相位變動式記憶體(Phase Change Random Access Memory － PCM、PCRAM)由於具有非易失性、好的擴展性、低靜態功率消耗的優勢讓他有希望成為主記憶體，可是因為它的耐久力限制和寫入方面需要較高的能量和較長的延遲時間，想要完全取代動態隨機存取記憶體(Dynamic Random Access Memory - DRAM)是有困難性的。
為了隱藏這些缺點，目前的技術趨向建構DRAM-PCM的混合式記憶體，DRAM配置作為前端快取記憶體，而PCM作為後端主記憶體，可是使用小容量的DRAM快取會導致較高的資料存取失誤率，而引起PCM的存取次數增加，使得效能降低和能量的損耗。
本論文中，我們將提出混合式記憶體架構的適應性分頁與緩衝區機制，在整合不同記憶體晶片架構上，考慮到混合式記憶體晶片間不同的讀寫特性、存取耗能和存取延遲等特性，進行Page Allocation演算法，來調整不同Task所使用的記憶體區塊大小，進而增加DRAM快取使用率，藉由實驗結果證明，我們的方法可以有效的提升混合式記憶體的效能和使用壽命。

關鍵字

混合式記憶體 ； 適應性分頁 ； 緩衝區機制

並列摘要

Owing to the advantages of non-volatility and low static energy consumption, Phase Change Random Access Memory (PCM or PCRAM) can become the mainstream memory device. However, it is a little bit of difficult that the PCM limited by endurance, high write-in power requirement and access latency want to replace Dynamic Random Access Memory (DRAM).
Therefore, to obtain better performance, the development of memory device would tend to be built in the form of DRAM-PCM Hybrid Main Memory architecture. The configuration of the total device will be allocated by the front-end DRAM and the back-end PCM. The DRAM and the PCM are served as a flash memory and main memory, respectively. But, the hybrid device using small capacity DRAM cache will cause the higher miss rate in data access. In addition, the PCM part will increase the frequency of data access. Then, the hybrid device will show low efficiency and leakage power consumption.
In this thesis, we will propose the adaptability page and buffering mechanism of DRAM-PCM Hybrid Memory architecture. While in the combing different chips, the difference of read-write feature, access latency, and access power consumption features between the hybrid chips would take into consideration and conduct Page Allocation Algorithm to adjust the capacity for the different Task to improve DRAM cache efficiency. According to the experiment results, our method can improve the efficiency of DRAM-PCM Hybrid Memory device and prolong its lifetime.

並列關鍵字

DRAM-PCM hybrid memory ； page allocation ； buffering mechanism

參考文獻

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