堆疊式高介電係數阻擋層對電荷陷阱式快閃記憶體元件的影響

當浮動式閘極結構之快閃記憶體無法滿足元件微縮的發展時，SONOS-Type是取代浮動閘極結構的熱門候選者之一。而SONOS元件的穿遂氧化層厚度則大約是30，就這樣的厚度而言，對於元件在可靠度方面的品質來說就會是一個問題，亦即，要如何在不改變穿遂氧化層厚度的前提之下，仍然能夠讓元件具有十年以上的電荷留存能力?並且在不犧牲資料留存能力的要求下在電性方面能有所提升，這些都是目前急需克服的問題。本實驗將利用不同高介電係數材料以堆疊方式堆疊出SONOS元件的阻擋氧化層，研究主要是利用不同的材料具有不同的特性，配合堆疊式的結構，藉由不同的氮化程度、能隙大小的改變，K值的影響，堆疊厚度的改變等種種原因，利用能帶工程堆疊出最恰當的阻擋氧化層。由實驗結果得知，以Al2O3/HfAlO結構做為阻擋氧化層，即先疊LOW-K再疊HIGH-K的阻擋層結構會有較佳的元件效能，以能隙觀點來看，第一層阻擋層先疊能隙較大的材料，第二層再疊K值較大，厚度較大的材料，可使得元件效能提升。同樣的，先疊一層高品質之二氧化矽再搭配不同的高介電係數做為阻擋氧化層，其元件特性也會表現得更好。實驗結果也可得知，元件經由PIII氮化技術可以減少HfO2材料在退火後之結晶化問題，進而提升電荷保持力，提升元件可靠度。

關鍵字

阻擋層；堆疊式

並列摘要

When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important. In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer. For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide(low-k/high-k),a lower operation voltage can be achieve. Using Al2O3/HfAlO as blocking layer has better performance than other stacked structures. Take high bandgap material as first layer blocking layer ,and secondly stack higher k material can improve device performance. Stacking a high quality film as blocking layer first and then stack various high-k materials by PIII nitrogen treatment can reduce crystallize and enhance retention , promote device reliability after high temperature annealing process.

並列關鍵字

FLASH ； CTF

參考文獻

[1] Chih-Hao Cheng and Joseph Ya-Min Leea et al.,”Metal/high-k/high-k/oxide /semiconductor capacitors and field effect transistors using Al/La2O3/Ta2O5 /SiO2 /Si structure for nonvolatile memory applications,”Applied Physics Letter,91,pp.192903~192903-3,2007

[2] S. Choi, M. Cho, H. Hwang et al., “Improved metal oxide nitride oxide silicon type flash device with high-k dielectrics for blocking layer,” Journal of Applied Physics, vol. 94, no. 8, pp. 5408-5410, Oct, 2003.

[3] J. Sanghun, H. Jeong Hee, L. Junghoon et al., “Impact of metal work function on memory properties of charge-trap flash memory devices using fowler-nordheim P/E mode,” Electron Device Letters, IEEE, vol. 27, no. 6, pp. 486-488, 2006.

[4] Jiankang Bu, et al., “Retention reliability enhanced SONOS NVSM with scaled programming voltage”, IEEE Aerospace Conference paper, Vol.5, P5-2383 5-2390,2001

[6] W. J. Tsai, et al., “Data retention behavior of a SONOS type two-bit storage flash memory cell”, IEEE International Electron Devices Meeting, Page(s): 32.6.1 - 32.6.4 ,2001

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堆疊式高介電係數阻擋層對電荷陷阱式快閃記憶體元件的影響

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