一個使用嵌入式有限脈波響應濾波器的60億赫茲除小數頻率合成器

A 6 GHz Fractional-N Frequency Synthesizer Using Embedded FIR Filter Technique

盧泓諭(Hung-Yu Lu)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2011年)

https://doi.org/10.6342/NTU.2011.10250

摘要

近來，隨著越來越多傑出的研究成果，全數位鎖相迴路已然變為一個當紅的研究主題。跟傳統類比電路使用充電汞的架構相比，全數位的架構有著以下的強勢優點：容易在不同製程之間做電路轉換、小面積、先進製程的高電路成果表現以及易與數位電路系統整合等好處。為了更進一步發展全數位鎖相迴路的潛力，在本篇論文中我們完成兩個跟全數位鎖相迴路有關的架構設計。
在第一顆晶片中，一個使用嵌入式有限脈波響應濾波器的60億赫茲除小數頻率合成器的設計被提出，用以抑制傳統的除小數頻率合成器中，受限於量化雜訊的問題。其根本概念是利用調變器與振盪器的資訊，經由數位電路的運算，來補償主迴路上所產生的量化誤差，因此得以節省許多晶片面積及電功率消耗。實驗的晶片是使用台積電90奈米的互補式金氧半場效電晶體製程，量測的結果在使用所提出的演算法下，量化雜訊在輸出端的相位雜訊被壓抑了15dB，晶片中的電路面積占了0.18 mm2 ，而功率消耗為28.8mW.
在第二顆晶片中，我提出了一個使用串接式架構的全數位鎖相迴路，輸出的頻率為134百萬赫茲。在這顆晶片中，我利用串接式的架構搭配上注入式鎖像迴路的觀念，藉此消除在單一迴路中，迴路頻寬受限於輸入頻率過低，而產生的相位雜訊過高的問題。實驗的晶片是使用台積電180奈米的互補式金氧半場效電晶體製程。

關鍵字

全數位鎖相迴路 ； 頻率合成器

並列摘要

All-digital phase-locked loop (ADPLL) has recently become more and more popular since it emerges as an attractive alternative to the traditional analog PLL. As comparing with the conventional Charge-pump PLL (CPPLL), the all-digital implemented circuits have the advantage of high portability, small area, high performance in the advanced process, and better integrity in digital system. To develop the potential of ADPLL in more aspects, two chip work base on the ADPLL structure is realized.
In the first work, a 6-GHz All-digital phase-locked loop (ADPLL) based fractional-N frequency synthesizer using embedded FIR filtering technique for delta-sigma modulator (DSM) quantization noise suppression is presented. The basic concept of the algorithm is to use the information from DSM and digitally-controlled oscillator (DCO) period to predict the virtual dividers & phase-frequency detectors (PFDs) output and then compensate the error term in front of the digital-loop filter (DLF). As a result, saves large chip area, as well as power dissipation by the algorithm. The experimental chip is fabricated in a 90 nm 1P9M CMOS process. With the proposed FIR filtering algorithm, the out-of-band DSM quantization noise is suppressed by about 15 dB. The core area is 0.18 mm2 with total power consumption equal to 28.8mW.
In the second chip work, a 134-MHz ADPLL using cascaded structure is proposed. The biggest problem in this work is due to the limitation of loop bandwidth (Fref/10), as a results, the DCO noise dominate the total noise flow. To solve the problem, a cascaded PLL structure accompanied with the implementation of sub-harmonic injection-locked PLL in the first stage, hoping to improve the noise performance as comparing with the single stage PLL. The experimental chip is fabricated in a 0.18 um 1P6M CMOS process.

並列關鍵字

ADPLL ； FIR ； frequency synthesizer

參考文獻

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