低傳輸延遲二維晶片網路之星狀架構

半導體的製程已經縮小到32奈米而且還會愈來愈小，在此同時智產 (intellectual properties)核心的數目不斷增加。隨著晶片製程技術的演進，如今在單一晶片上可以涵蓋數以億計個邏輯閘，所以晶片系統(System on a Chip)的設計能夠放入龐大數量的智產核心。為了得到更好的性能，在設計晶片系統時晶片通訊架構是個很重要的議題。然而如何在各智產核心之間進行訊息交換又衍生出新的研究題目，近年晶片網路(Network on chip)架構被提出用來解決複雜的晶片系統難題，由於它擁有良好的延伸性以及可信懶的晶片傳輸模式，現今在學術界及工業界都廣泛的採用。晶片網路採用單純的路由演算法，而且擁有優秀的網路延展性，所以在過去的晶片網路設計中廣泛的使用2D網格(mesh)拓墣架構的晶片網路。然而2D網格拓墣相較之下有較寬的網路半徑，因此有些封包在長距離傳輸時會有較多的延遲。在這篇論文中我們藉由讓較長距離的封包在另一層網格上傳輸，相對於傳統的2D網格拓墣是一個簡易的設計方法。實驗則採用一個長寬為12 × 12的星狀架構二維晶片網路，在3 × 3個節點為子網格的架構下，使用ORION 2.0 的功率面積模型去計算。並分別和一般以及雙層網格架構的二維晶片網路做比較。藉由模擬我們得到星狀網路架構能降低長距離傳輸所需走的路徑。一個大小為12 × 12 的星狀架構二維晶片網路的面積功率路徑乘積和傳統的網格架構比較能減少17.2%，而和雙層網格架構相比則減少了10.3%。

關鍵字

晶片網路；晶片系統；星狀；網格；低延遲

並列摘要

The size of semiconductor technology is reducing to 32 nm and is getting smaller. At the same time the intellectual properties (IP) cores is increasing. With the progressing of deep submicron chip technology, we can put billions of transistors on a single chip nowadays. Therefore System on Chip (SoC) designs will be able to put large numbers of IP cores on one chip. On chip communication architectures becomes an important issue in System on Chip (SoC) design in order to get a better performance. Lately Network on Chip (NoC) has been brought up to solve complex SoC communication problems and is now widely accepted by academe and industry due to its better scalability and reliability. The 2D mesh NoC has simple routing algorithm and good network scalability therefore becomes a well-liked topology of earlier NoC designs. While some packet with large distance traffic may have higher transmission latency due to the comparatively long average distance between any different two nodes in a 2D mesh. We propose a simple design method for 2D mesh NoC called Star Type architecture in this thesis. The basic concept is to let the packets with large distance traffic travel on an extra second level mesh. The experiment environment is using a 12 × 12 Star Type NoC, which is divided by 3 × 3 sub-mesh. We use the ORION 2.0 power and area model to simulate. Simulation results demonstrate that it can reduce the hops traversed for long distance traffic. And the product of area, power and hop counts of Star Type 12 × 12 mesh can be decreased by 17.2%, and 10.3% compared to normal mesh architectures and 2-Level mesh, respectively.

並列關鍵字

NoC ； Network on Chip ； System on Chip ； Star Type ； Mesh ； Low Latency

參考文獻

[1] G. d. Micheli and L. Benini, Networks on Chips: Technology and Tools: Morgan Kaufmann, 2006.

[2] L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, vol. 35, pp. 70-78, 2002.

[3] W. J. Dally and B. Towles, "Route packets, not wires: on-chip interconnection networks," in Design Automation Conference, 2001. Proceedings, 2001, pp. 684-689.

[4] A. Mello, et al., "Virtual Channels in Networks on Chip: Implementation and Evaluation on Hermes NoC," in Integrated Circuits and Systems Design, 18th Symposium on, 2005, pp. 178-183.

[6] L. Benini and G. D. Micheli, "Powering networks on chips: energy-efficient and reliable interconnect design for SoCs," presented at the Proceedings of the 14th international symposium on Systems synthesis, Montreal, P.Q., Canada, 2001.

國際替代計量

低傳輸延遲二維晶片網路之星狀架構

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