V頻段使用變壓器耦合之次諧波正交混頻器及緩衝放大器

V-band Subharmonic IQ Mixer Using Transformer Coupling and Buffer Amplifier

陳星羽(Hsing-Yu Chen)

指導教授 ： 盧信嘉

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2016年)

https://doi.org/10.6342/NTU201603035

摘要

本論文主要研究V頻段射頻通訊系統接收路徑上之緩衝放大器及降頻次諧波混頻器，本論文首先介紹緩衝放大器設計原理，簡介不同設計目的之緩衝放大器拓樸的選擇。再來介紹不同混頻器之功能與架構，包含主動式與被動式、單平衡式及雙平衡式。最後介紹不同次諧波混頻器之功能與架構，亦包含主動式及被動式，其中以次諧波吉伯特混頻器較被廣泛運用。
本論文提出一個兩級串級放大器架構之緩衝放大器，使用疊接放大器串接共源極放大器，可順利實現一低功耗、高線性度、低雜訊之緩衝放大器。之後提出一改良之單平衡式次諧波混頻器，利用倍頻器將本地震盪端訊號倍頻，並加上主動負載交叉耦合對來提升轉換增益，並使用變壓器耦合提高電路線性度。最後提出一改良之次諧波吉伯特混頻器，同樣利用變壓器耦合提高電路線性度，並於輸出端加入轉阻放大器，使混頻器對下一級電路輸入阻抗較不敏感，可解決電路震盪的可能性。
本論文緩衝放大器利用TSMC 40nm CMOS製程，晶片尺寸為 ，量測結果增益壓縮2 dB頻寬為51.9 GHz至62 GHz，小訊號增益為9.92 dB，雜訊指數最低於頻率59 GHz時為4.8 dB，輸入P1dB為-13 dBm，IIP3為-0.5 dBm，直流功耗為11.23 mW，與模擬結果相比增益及中心頻率點不如預期，其原因為電晶體模型於高頻時需做修正，於本論文第6章會詳細介紹。
使用倍頻器之次諧波正交混頻器利用TSMC 90 nm CMOS製程，晶片尺寸為 ，量測結果轉換增益為-20.5 dB，輸入P1dB為1 dBm，本地震盪功耗為11 dBm，直流功耗為13.92 mW，與模擬結果相比轉換增益差異較大，其原因於本論文第6章會詳細介紹。使用變壓器耦合之正交混頻器利用TSMC 40nm CMOS製程，晶片尺寸為 ，其晶片還未製作完畢，模擬結果轉換增益為-13 dB，輸入P1dB為-5 dBm，IIP3為4 dBm，本地震盪功耗為7 dBm，中頻增益降1 dB頻寬為0.01 GHz至1 GHz，直流功耗為26.62 mW。

關鍵字

次諧波混頻器 ； 正交混頻器 ； 變壓器耦合 ； 交叉耦合對 ； 主動負載 ； 轉阻放大器 ； 單平衡式混頻器 ； 吉伯特混頻器

並列摘要

In this thesis, a buffer amplifier and two subharmonic down-conversion mixers for V-band communication receiver system are designed and fabricated. This thesis starts from introducing buffer amplifier design principles. Then, this thesis introduces different mixer topologies and features, including active, passive, single balanced and double balanced mixers. Finally, this thesis introduces different sub-harmonic mixer topologies and features. Among all the sub-harmonic mixer topology, the sub-harmonic Gilbert cell mixer is the most widely used.
This thesis proposes a two stage cascade amplifier using cascode amplifier with common-source amplifier, and successfully implement a low-power, high linearity and low noise buffer amplifier. Then, we propose an improved single balanced harmonic mixer. This mixer uses frequency multiplier to double local oscillation frequency, active load of cross-coupled to enhance conversion gain, and transformer to improve linearity. Finally, this thesis proposes an improved sub-harmonic Gilbert cell mixer, also using transformer to improve linearity, and adding transimpedance amplifier at output stage to reduce sensitivity to next stage’s impedance, and avoid circuit oscillation.
In this thesis, buffer amplifier is developed in TSMC 40 nm CMOS technology. The measured 2dB bandwidth is 51.9GHz to 52GHz, and small signal gain is 9.9dB. The minimum noise figure is 4.8dB at 59GHz, input P1dB is -13dBm, IIP3 is -0.5 dBm, and DC power consumption is 11.23mW. The measured results comparing with simulated results have some deviation, due to in-accurate transistor model at high frequency.
The sub-harmonic IQ mixer is developed in TSMC 90 nm CMOS technology. The measured conversion gain is -20.5dB, the input P1dB is 1dBm, and the DC power consumption is 13.92mW. The measured results comparing with simulated results have some deviation, and the reason is explained in Chapter 6. Finally, the sub-harmonic IQ mixer using transformer is developed in TSMC 40 nm CMOS technology. This chip is still under fabrication. The simulated conversion gain is -13 dB, input P1dB is -13dB, IIP3 is 4dBm, and DC power consumption is 26.62mW.

並列關鍵字

sub-harmonic mixer ； IQ mixer ； transformer coupled ； cross-coupler ； transimpedance amplifier ； single balanced mixer ； Gilbert cell mixer

參考文獻

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