高速低功率之管線式類比數位轉換器

High Speed, Low Power Pipeline Analog-to-Digital Converter

曾千鑑(Chien-Jian Tseng)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2016年)

https://doi.org/10.6342/NTU201610501

摘要

導管式類比數位轉換器普遍被採用在眾多高速、中高解析度的應用上。在導管式類比數位轉換器的設計中，通常使用了一個高增益、高頻寬的運算放大器對前一級的殘餘訊號做放大，而這一個運算放大器的規格在某種程度上也就決定了整個導管式類比數位轉換器的性能表現，同時運算放大器也消耗了大部分的功耗。
然而在現今的先進製程下，主動元件本身的本質增益下降，伴隨著愈低的供電電壓，再再使得高增益、高頻寬運算放大器的設計變成導管式類比數位轉換器設計上的瓶頸與挑戰。因此，解決運算放大器的問題便成了當今設計高速、低功耗導管式類比數位轉換器的熱門課題。
本篇論文提出了四個創新性的導管式類比數位轉換器設計。在第四章的兩個晶片設計應用了非完全穩態的技巧，因此，使用了低增益、低頻寬的運算放大器以節省功率消耗。而非完全穩態導致的殘餘訊號放大誤差則透本論文所提出的取點時間校正及次基數還原等方法來消除。在第五章中，本論文則進一步的延伸了共用電容的設計概念以減低運算放大器的輸出端電容負載，達到省電的目的。在這兩章節中的晶片設計仍然是基於運算放大器的使用。在第六章中，本論文則提出了一個操作在時間領域上對殘餘訊號做放大的方法，能進一步的免除運算放大器的使用，而仍能實現導管式類比數位轉換器的設計。

關鍵字

導管式類比數位轉換器 ； 低功耗 ； 非完全穩態 ； 共用電容 ； 時間領域

並列摘要

Opamp is a critical and power-hungry block in high performance pipeline ADC design. Unfortunately, opamp design is getting challenging in advanced deep submicron process. The techniques proposed in the dissertation aim to ease opamp design effort or simply remove opamp usage in pipeline ADC design.
The first and second designs employ incomplete settling technique to realized high speed ( > GS/s ) pipeline ADC design. Two novel design concepts, sampling point calibration and sub-radix conversion, are adopted to calibrate stage gain error. Thus, low gain and low bandwidth opamps can be used in pipeline ADC design to save power consumption.
The third design extends the usage of capacitor sharing technique, not only between the 1st and 2nd MDACs but also between the 2nd and the 3rd MDACs. By reducing the effective capacitance loading at opamp output node, the bandwidth requirement of the opamp can be loosen.
The final design tries to get rid of opamp usage in the pipeline ADC design. The MDAC function, i.e. subtraction and amplification, can be realized by merely constant charging current source, capacitors and comparators. In addition, processing signal in time domain instead of in voltage domain takes advantage of increasing timing resolution in advanced process and thus fits the process trend.

並列關鍵字

pipeline ADC ； power efficiency ； incomplete settling ； capacitor sharing ； time domain

參考文獻

[1] Y. S. Shu, “A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators” in Symp. VLSI Circuits Dig., Jun. 2012, pp.26-27.

[2] Y. S. Hu, C. Y. Shih, H. Y. Tai, H. W. Chen and H. S. Chen, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s subranging SAR ADC in 40nm CMOS” in Asian Solid-State Circuits Conf., pp. 81–84, Nov. 2014.

[3] D.W. Cline and P.R. Gray, "A power optimized 13-b 5M Samples/s pipelined analog-to-digital converter in 1.2μm CMOS," IEEE J. Solid-State Circuits, vol.31, no.3, pp.294-303, Mar 1996.

[5] W. Yang, D. Kelly, I. Mehr, M.T. Sayuk, adn L. Singer, “A 3-V 340-mW 14-b 75-MS/s CMOS ADC with 85-dB SFDR at Nyquist input,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1931-1936, Dec. 2001.

[7] T. Sepke, P. Holloway, C. Sodini, and H.S. Lee, “Noise analysis for comparator-based circuits,” IEEE Transactions on Circuits and Systems I-Regular Papers, vol. 56, no. 3, pp. 541-553, Mar. 2009.