實現十位元五十百萬赫茲之導管式類比數位轉換器

在本論文中，我們提出了一個十位元五十百萬赫茲的導管式類比數位轉換器，並利用其較寬的頻帶可應用在IEEE 802.11 a 無線通訊系統或數位電視上。在整體的架構上採用的是每階段實現1.5 位元並結合數位錯誤修正技術來達到所需要的規格。所提出的導管式類比數位轉換器的微分非線性誤差(DNL)和積分非線性誤差(INL)分別在± 0.45 LSB和± 0.46 LSB的範圍內。在取樣頻率為五十百萬赫茲、輸入頻率為五百萬赫茲和雙端輸入電壓範圍為0.65伏特~1.85伏特時經過Hspice所模擬的訊號雜訊動態比(SNDR)為60.5dB而有效位元(effective number of bits)則為十位元。當供應電壓為2.5伏特、取樣頻率為五十百萬赫茲時，對於所有電路所測量到的功率消耗為93mW，此研究所提出的導管式類比數位轉換器在0.35微米2P4M標準互補式金氧半製程下完成並交送給國家晶片中心完成下線，整個晶片的面積不含PADs為2.8×1.5 mm2。

關鍵字

類比數位轉換；導管式；取樣與保持

並列摘要

In this paper, a 10-bit 50MSample/s Nyquist-rate CMOS pipelined analog-to-digital converter (ADC) with digital correction is presented for the IEEE 802.11a WLAN and HDTV applications. The digital correction technique adapted by this pipelined ADC can give more accurate demands in application. The simulated DNL and INL of the presented pipelined A/D converter are suppressed within ± 0.45 LSB and ± 0.46 LSB, respectively. The simulated SNDR is 60.5dB and the effective number of bits is 10 at the rate of 50MSample/s with a 5MHz input frequency. This presented circuit has been fabricated in a 0.35um 2P4M CMOS process. The dissipation power of 93mW in this ADC was measured under the sampling rate of 50MHz at 2.5V supply voltage. And its core area without PADs is 2.8×1.5 mm2.

並列關鍵字

Analog-to-Digital(A/D) ； Pipelined ； sample-and-hold

參考文獻

[1] Yotsuyanagi, T. Etoh, and K. Hirara, “A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Circuits, IEEE Journal of, Vol. 28, Issue: 3, pp. 292–300, Mar 1993.

[4] R. J. Baker, CMOS Mixed-Signal Circuit Design, IEEE press, 2003..

[7] K. Balasubramanian, “A flash ADC with reduced complexity,” Industrial Electronics, IEEE Transactions on Volume 42, Issue 1, pp. 106-108, Feb. 1995.

[8] Yotsuyanagi, T. Etoh, and K. Hirara, “A 10 b 50 MHz pipelined CMOS A/D converter with S/H,” Solid-State Cir cuits, IEEE Journal of, Vol. 28, Issue: 3, pp. 292–300, Mar 1993.

[9] D. A. Johns, K. Martin, ”Analog Integrated Circuit design,” 1997.

國際替代計量

實現十位元五十百萬赫茲之導管式類比數位轉換器

全文下載

主題瀏覽