使用結構化客製晶片實現基於SoC平台的OpenRISC 1200處理器

Implementation of OpenRISC 1200 Based SoC Platform using Via-Configurable Structured ASICs

謝宗翰(Tsung-Han Hsieh)

指導教授 ： 林榮彬

元智大學/資訊學院/資訊工程學系/碩士(2011年)

https://doi.org/10.6838/YZU.2011.00355

摘要

現今的數位積體電路設計，可分為場效可程式化邏輯閘陣列(FPGA)和半客製化積體電路設計(Cell-based/Standard cell ASIC)。然而對於設計者來說，FPGA容易設計、設計週期短，且有較低的NRE費用，但相較於ASIC來說，FPGA消耗的功率高、單位成本高且效能較低。為了在IC設計的成本和效能間取得平衡，因此出現一個新的設計方法，稱作結構化客製晶片(Structured ASIC)，它結合FPGA和ASIC的優點，以極具競爭力的單位成本提供優秀的矽晶片性能。
在這篇論文裡，使用我們自己提出的可配置導孔邏輯區塊(Via-Configurable Logic Block)建立標準元件庫，透過一些商業輔助軟體，實現基於SoC平台的OpenRISC 1200處理器，我們的晶片面積是13 mm2，操作頻率可達90 MHz，功率消耗約為1519毫瓦。

關鍵字

結構化客製晶片 ； 處理器

並列摘要

Digital integrated circuit design can be done using field programmable gate array (FPGA) or semi-custom standard cell design approach. Designers can more easily realize their designs using FPGA than using standard cell design approach. FPGA enables shorter design cycle, and lower NRE costs. But FPGA incurs higher power consumption, higher unit cost and lower performance than ASIC does. In order to strike a balance between cost and performance in IC design, a new design technology, known as Structured ASIC, that takes advantage of FPGA and ASIC was invented. Structured ASIC can attain good silicon performance with a competitive unit cost.
In this paper, we use our Via-Configurable Structured ASIC technology to design a standard cell library using some commercial tools. We use this library to implement a SoC platform based on OpenRISC 1200 CPU core. Our implementation is based on a typical 0.18um process. The experimental result shows that chip operating frequency can achieve 90 MHz with 13 mm2 area and 1519mW power consumption.

並列關鍵字

ASIC ； OpenRISC ； SoC

參考文獻

[2] B. Zahiri, “Structured ASICs: opportunities and challenges,” ICCD, 2003, pp. 404-409.

[3] K. C. Wu, Y. W. Tsai, “Structured ASIC, evolution or revolution?” ISPD, pp.103-106, 2004.

[4] L. Pileggi et al., “Exploring regular fabrics to optimize the performance-cost trade-off,” DAC, 2004, 782-787.

[5] N. V. Shenoy, J. Kawa, R. Camposano, “Design automation for mask programmable fabrics,” DAC, 2004, pp. 192-197.

[6] C. Patel, A. Cozzie, H. Schmit, and L. Pileggi, “An architectural exploration of via patterned gate arrays,” ISPD, 2003, pp. 184–189.