半導體可製造性設計之資料挖礦架構及其實證研究

A Data Mining Framework of Design for Manufacturability in Semiconductor Manufacturing and its Empirical Study

許嘉裕(Chia-Yu Hsu)

指導教授 ： 簡禎富

國立清華大學/工學院/工業工程與工程管理學系/博士(2009年)

https://doi.org/10.6843/NTHU.2009.00015

摘要

在全球半導體業越來越激烈的競爭之下，半導體廠必須藉由良率提升、生產力提升以及成本降低以維持競爭優勢。隨著尺寸的緊縮與積體電路技術進入至奈米世代，越來越複雜的製造過程也導致產品的低良率。然而，低良率的問題難藉由改善製造過程而完全解決，其中有大部分必須藉由改善積體電路之設計從源頭做起。設計者必須具備晶圓製造相關的領域知識，以確認積體電路設計因子與製造反應因子的因果關係。然而，設計者往往並非製造上的專家，有些關係並無法直接透過物理關係或複雜的數學方程式架構。在晶片設計與晶圓製造的過程中均會產生與紀錄大量的資料，而這些資料中可能隱含著有意義的資訊。本研究目的係提出一可製造性設計之資料挖礦架構，利用資料挖礦方法建構設計因子與製造反應因子之因果關係，作為晶片佈局之設計指導規則基礎，以獲得較佳之可製造性。所萃取之樣型或歸納之規則更可進一步作為設計者驗證其假設或提供設計改善方向。本研究藉由晶圓生產力提升與良率提升之實證研究以驗證本架構之效度與實際可行性。研究結果發現本研究架構可協助晶片設計者取得較佳之晶片佈局設計，以提升晶圓生產力，並且提供一套指導原則，在考慮量測成本與補償成效下，建議設計者規劃量測覆蓋誤差之佈局，以提升曝光之良率。

關鍵字

可製造性設計 ； 資料挖礦 ； 積體電路設計 ； 良率提升 ； 晶圓生產力 ； 半導體製造

並列摘要

As global competition continues to strengthen in semiconductor industry, semiconductor companies strive to maintain competitive advantages through yield enhancement, productivity improvement, and cost reduction. As the shrinking feature size and the advanced technology of integrated circuit (IC), the impact of unpredictable variations of manufacturing process are increasing and leading to low yield. The low yield problem can hardly be solved by manufacturing process improvement alone, while it can be improved by design of chip modification. In particular, cause-and-effect relationship between IC designable variables and manufacturing response variables should be identified in advance. However, some of them cannot be formulated directly by physical or mathematical formula. In particular, amounts of data have been recorded during design and manufacturing process, yet meaningful information is latent behind the huge data. This study aims to develop a data mining framework of design for manufacturability (DFM), in which data mining methodology is applied to construct the casual relation as the basis of design guidelines to improve chip layout with better manufacturability. The extracted patterns or derived rules can not only help designer to validate the assumption of design variable but also be a basis of further improvement direction. Finally, two empirical studies for enhancing wafer productivity and yield were conducted to evaluate the validity of proposed framework and practical viability. The proposed framework can assist IC designer in effectively deriving chip layout design for wafer productivity enhancement. In addition, it also can provide a guideline of overlay registration layout for exposure yield enhancement with metrology cost and compensation performance taken into account.

並列關鍵字

design for manufacturability ； data mining ； IC design ； yield enhancement ； wafer productivity ； semiconductor manufacturing

參考文獻

Allan, G. A., Walton, A. J., and Holwill, R. J. (1992), “An yield improvement technique for IC layout using local design rules,” IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 11, pp. 1355-1362.

Backus, P., Janakiram, M., Mowzoon, S., Runger, G. C., and Bhargava, A. (2006), “Factory cycle-time prediction with a data-mining approach,” IEEE Transactions on Semiconductor Manufacturing, Vol. 19, No. 2, pp. 252-258.

Batista G. E. and Monard, M. C. (2003), “An analysis of four missing data treatment methods for supervised learning,” Applied Artificial Intelligence, Vol. 17, No. 5-6, pp. 519-533.

Beasley, J.E. (1985), “Algorithm for unconstrained two-dimensional guillotine cutting,” Journal of the Operational Research Society, Vol. 36, No. 4, pp. 297-306.

Bode, C.A., Ko, B.S., and Edgar, T.F. (2004), “Run-to-run control and performance monitoring of overlay in semiconductor manufacturing,” Control Engineering Practice, Vol. 12, No. 7, pp. 893-900.