非零時序差異時鐘樹的設計自動化系統

隨著製程技術的進步，尤其在進入深次微米製程後，時鐘樹變成主要影響電路效能、電路可靠度和功率消耗的主要因素。雖然有效的利用暫存器間的時序差異可以提昇電路效能、電路可靠度和降低功率消耗，但是，在常見的商業軟體中，並沒有利用暫存器間的時序差異，而是零時序差異或一個固定的時序差異。因此，我們在本篇論文提出了一個非零時序差異時鐘樹的設計方法，並且用ECO與現有的電腦輔助設計流程整合。我們的設計方法不但可以增加電路的效能和電路的可靠度，也可降低功率的消耗和晶片的面積。我們以商用佈局軟體所合成的時鐘樹為初始架構，再利用更換邏輯閘大小的演算法，在重覆取樣和零取樣的限制下，去最佳化我們的時鐘樹。本文所提出的演算法已用C/C++程式實現，測試檔的結果顯示出我們所提出的方法確實可以增加電路效能和電路可靠度，減少功率消耗和面積。

關鍵字

零取樣；時鐘樹；時序差異；更換邏輯閘；深次微米製程；重覆取樣

並列摘要

As the process technology enters the deep sub-micron design era, the design of clock tree has become one of the primary factors limiting circuit performance, process-variation-tolerant and a major source of power dissipation. Although the clock skew between registers has been previously recognized as a manageable resource, the objective of commercially available layout tools is zero skew or a fixed skew bound. In this thesis, we will present a practical non-zero skew clock tree design methodology, which can be incorporated into ECO stage of the existing ASIC design flow. Our design methodology can not only increase the circuit performance and the circuit reliability, but also decrease the power dissipation and area. Given an initial clock tree, which is synthesized by commercially available layout tool, a gate-sizing algorithm is proposed to optimize the clock tree under the constraint that the double and zero clocking hazards do not occur. The proposed algorithm has been implemented in a C program. Benchmark data consistently shows that our design methodology achieves very good results in terms of the performance enhancement, reliability enhancement, power reduction and area decrease.

並列關鍵字

double clocking ； clock tree ； zero clocking ； skew ； deep sub-micron design ； gate-sizing

參考文獻

[1] J.P. Fishburn, “Clock Skew Optimization”, IEEE Trans. on Computers, Vol. 39, No. 7, pp. 945—951, 1990.

[3] M.B. Maaz and M.A. Bayoumi, “A Non-zero Clock Skew Scheduling Algorithm for High Speed Clock Distribution Network”, in the Proc. of IEEE International Symposium on Circuits and Systems, Vol.6, pp. 382—385, 1999.

[5] Avant! Inc., “IC Layout Getting Started Guide”, 1995.

[12] J. Oh and M. Pedram, “Power Reduction in Microprocessor Chips by Gated Clock Routing”, in the Proc. of IEEE ASP-DAC, pp. 313—318, 1998.

[13] R. ader, E.G. riedman, A. Litman and I.S. Kourtev, “ Scale Clock Skew Scheduling Techniques for Improved Reliability of Digital Synchronous VLSI Circuits”, ISCAS 2002. Circuits and Systems, Vol. 1, pp I-357—I-360 vol.1.

國際替代計量

非零時序差異時鐘樹的設計自動化系統

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