應用於多頻帶正交多工超寬頻系統之高速類比至數位轉換器電路設計

本論文提出取樣週期為900ps的六位元高速暨低功率的快閃式類比至數位轉換器(Flash ADC)電路，而此電路是應用在多頻帶正交多工超寬頻(MB-OFDM UWB)通訊系統的接收端電路中。在低功率電路設計上，本論文中所提出的設計方法具有以下三個功效：(一)降低動態再生型比較器與動態邏輯電路的充電電流、(二)降低各個電路的負載電容量、(三)減少數位電路的輸出邏輯轉態次數。而論文中所提出的電路能在不嚴重影響操作速度的情況下，大幅降低Flash ADC電路的消耗功率。在Flash ADC電路的子電路中，本論文是改良比較器陣列與溫度計碼至二進位碼編碼器的效能。對於比較器陣列，所提出的方法是採用較低的供應電壓降低比較器的充電電流。在編碼器電路中，除了利用較低的供應電壓之外，還使用了反相器陣列來降低比較器陣列的負載電容以及減少1-of-N編碼器的輸出邏輯轉態次數。本論文中在電路模擬上是使用TSMC公司所提供的CMOS 1P6M 0.18µm製程，而所採用的模擬軟體為Spectre。模擬結果顯示所提出的Flash ADC電路能在取樣週期為900ps下正常運作。而此電路操作在取樣頻率為1GHz時，其消耗功率僅為18.28mW。

關鍵字

比較器；溫度計碼至二進位碼編碼器； 1-of-N編碼器；快閃式類比至數位轉換器；多頻帶正交多工超寬頻通訊系統

並列摘要

This thesis proposes a 6-bit high speed and low power flash ADC with sampling period of 900ps and this circuit is utilized in the receiver of MB-OFDM UWB system. In low power circuit design, the design method proposed in this thesis has three effects: (1)reduce the charge current of dynamic regenerative comparator and dynamic logic circuit, (2)lower down the load capacitance of each circuit, (3)reduce the number of output logic transitions in digital circuits. The circuits proposed in this thesis can largely reduce the power consumption of flash ADC in the condition of not seriously affect the circuit operation speed. In the subcircuits of flash ADC, this thesis improves the performance of comparator array and thermometer code to binary code encoder. For comparator array, the proposed method is to apply a lower supply voltage to reduce the power consumption of comparator array. In the circuit of encoder, in addition to apply a lower supply voltage, an inverter array is also utilized to lower down the load capacitance of comparator array and reduce the number of output logic transitions in 1-of-N encoder. The circuit simulations in this thesis are based on TSMC CMOS 0.18µm process, and the simulation tool is Spectre. The simulation result shows that the proposed flash ADC can operate correctly in the sampling period of 900ps. As this circuit is operated in the sampling frequency of 1GHz, its power consumption is only 18.28mW.

並列關鍵字

MB-OFDM UWB System ； Flash ADC ； Comparator ； Thermometer Code to Binary Code Encoder ； 1-of-N Encoder

參考文獻

[1] S. Stroh, “Wideband: multimedia unplugged”, IEEE Spectrum, Vol.40, September 2003, pp.23~27

[3] A. Batra, J. Balakrishnan, G.R. Aiello, J.R. Foerster, A. Dabak, “Design of a multiband OFDM system for realistic UWB channel environments”, IEEE Microwave Theory and Techniques, Vol.52, September 2004, pp.2123~2138

[6] Quoc-Hoang Duong, T.-J. Park, E.-J. Kim, Sang-Gug Lee, “An all CMOS 743 MHz variable gain amplifier for UWB systems”, IEEE Circuits and Systems (ISCAS), May 2006, pp.21~24

[8] B. Razavi, “Principles of Data Conversion System Design”, Wiley-IEEE Press, 1995, pp.7~11,45~47,96~101

[9] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design 2ed”, Oxford University Press, 2002, pp.652~656

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應用於多頻帶正交多工超寬頻系統之高速類比至數位轉換器電路設計

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