中文摘要 高階合成主要將程式語言轉換至RTL level,其由於在高層次設計上驗證與模擬,能讓設計師有更多的時間與更充分的條件去進行設計空間探索或尋找更佳的解決方案。 本篇作者先前已進行過邏輯設計方面的高階合成部分研究,探討過程中發現於記憶體部分之效能影響,進而開始對記憶體方面做探討研究。由於在高階合成部分,主要的探討研究都還是以邏輯的最佳化為主,記憶體部分之高階合成研究,還是占少數。 相關研究指出,針對記憶體方面做最佳化,對效能以及能源消耗是有影響的,大部分演算法提出啟發式演算法來進行記憶體部分之最佳化,也有演算法結合了整數線性問題(ILP)與啟發式演算法進行最佳化。 本論文作者提出整數線性問題(ILP)與類似Kernighan–Lin 演算法之方式進行邏輯運算元以及記憶體部分之最佳化,最後並實際與利用bottom-up之演算法相必較,本論文提出之演算法,確實可以比使用貪婪演算法再更進一步最佳化,尋找出更好的解。
Abstract The main purpose of high level synthesis is to converting programming language into RTL level. In high-level design, designers could fully exploring design space and find a better solution. In the past, we have taken a lot of effect on logic design for high level synthesis, and found the performance impact of memory. Therefore, we explore research on memory performance during high level synthesis. However, most of previous work studies focus on logic resource optimize, few researches consider the impact of memory performance. Previous work on memory optimization also deal with the memory performance or power, some researches integrate heuristic algorithm and ILP formulation to get optimal solution. In this research, we integrate ILP formulation and Kernighan–Lin algorithm to optimize logic resource and memory performance. ILP formulation is applied for initial scheduling, and Kernighan–Lin algorithm is applied for module allocation and layer assignment. As shown in the experimental results, we compare our algorithm with bottom up algorithm, and better result in average.