全數位鎖相迴路設計和實現

DESIGN AND IMPLEMENTATION OF ALL DIGITAL PHASE-LOCKED LOOP CIRCUITS

謝承哲(Cheng-Che Hsieh)

指導教授 ： 詹耀福

大同大學/電機資訊學院/電機工程學系所/碩士(2010年)

摘要

鎖相迴路廣泛使用於現代的通訊系統，以往鎖相迴路的架構是基於類比技術建構而成，使用類比技術構成的鎖相迴路電路要整合在一個充滿雜訊的單晶片系統裡，這是一個不小的挑戰，另外類比技術的鎖相迴路也敏感於製程的改變；在不同的製程裡，通常電路元件的數值都必須重新設計過。換而言之，全數位鎖相迴路使用標準數位元件庫所設計， 電路架構中沒有使用晶片外元件(off-chip components)，因此，全數位鎖相迴路不敏感於製程的變化，對於溫度變化與雜訊也具有較高的容忍範圍。 本論文所提出的全數位鎖相迴路電路架構包含相位頻率偵測器、數位時間轉換器、遞迴式濾波器、數位控制振盪器以及除頻器，在本論文中我們使用一種新型架構的12-Bits數位控制振盪器以達到更好的解析度，最後經由電路模擬的結果，在參考訊號源為5MHz 時系統的鎖定時間為2.752 微秒，全數位鎖相迴路的操作頻率範圍為44MHz~510MHz， 最後使用ModelSim 6.0i驗證整個電路的可行性與功能性。

關鍵字

鎖相迴路 ； 全數位

並列摘要

A phase-locked loop (PLL) is a widely used circuit in modern radio communication systems. Traditionally, a PLL is made as an analog building block. However, integrating an analog PLL in a digital noisy systems-on-a-chip (SoC) environment is challenging. In addition, the analog PLL is sensitive to process parameters. It is too hard to use the same analog PLL design in different process. On the other hand, the ADPLL has no off-chip components. It is made from standard cells found in most digital standard cell libraries. Therefore, the ADPLL has the higher immunity for power supply noise, temperature, and process variation.
In this thesis, the ADPLL consists of a digital phase frequency detector, a digital loop filter, a digital controlled oscillator and frequency divider. This thesis proposed a new architecture of digital controlled oscillator has good performance in terms of fine resolution. The ADPLL are developed by Verilog, and they are simulated by ModelSim 6.0i to justify the feasibility of the proposed ADPLL .

並列關鍵字

Phase-Locked Loop ； ADPLL

參考文獻

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