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  • 學位論文

具功率因數修正與同步整流之低待機損耗電源供應器研製

Design and Implementation of a Low Standby Power Supply with Power Factor Correction and Synchronous Rectification

指導教授 : 歐勝源
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摘要


本篇論文主要是研製一高效率、低待機損耗之電源供應器。此電源供應器之結構包含電磁干擾濾波器,可以有效減少系統端雜訊所導致的電磁干擾問題。前級採用升壓型功率因數修正器,來提高功率因數,降低電流諧波,改善電力品質和諧波干擾。後級使用返馳式轉換電路,並搭配同步整流技術,使二次側功率損耗明顯降低,提高整體轉換效率。當輸出負載為極輕載時,脈波寬度調變控制器電路可關閉功率因數修正電路,減少功率因數修正級之損失;而當輸出為空載時,利用二次側待機模式控制電路將脈波寬度調變控制電路關閉,藉以明顯降低空載待機時的功率損耗。 最後本論文以輸入交流90 V~264 V、輸出直流電壓19 V、輸出功率90 W等為所提之高效率低待機損耗之電源供應器規格,實際完成並測試驗證確實可符合現今所有能源法規及能源之星規範的要求。

並列摘要


The purpose of the thesis is to develop a power supply with high efficiency and low stand-by power consumption. The power supply is constructed with an electromagnetic interference (EMI) filter which can efficiently reduce EMI issues caused by the system. The pre-stage adopts a boost Power Factor Corrector to increase the power factor and decrease the current harmonic, thus improves the power quality and harmonic issue. The post-stage adopts a flyback converter circuit and operates with a synchronous rectification technique. As a result, the power consumption on the secondary circuit has been significantly reduced and the efficiency of power supply can be raised. When the output loading is tiny, the pulse-width modulation control circuit can close power factor corrector circuit and diminish the loss of power factor stage. In addition, by closing the pulse width modulation stage on the stand-by mode control circuit will greatly decrease the stand-by power consumption under no-load condition. In conclusion, the thesis implements a high efficient power supply with low stand-by power consumption of which specifications include input voltage range of 90~264 Vac and output of 19 Vdc / 90 W. The practice power supply is implemented to test and verify the compliance with the of EPA requirements and Energy Star regulations.

參考文獻


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