一個高能源效率十二位元每秒取樣一億次之時間交錯連續漸進式類比數位轉換器使用共用半休眠切換技術

An Energy-Efficient 12b 100MS/s Time-Interleaved SAR ADC Using Shared Semi-Resting Switching Technique

林宜玄(Yi-Hsuan Lin)

指導教授 ： 謝志成

國立清華大學/電機資訊學院/電機工程學系所/碩士(2020年)

摘要

本論文提出一個使用共用半休眠切換技術以求高能源效率的12位元、每秒取樣1億次之時間交錯連續漸近式類比數位轉換器。
在物聯網應用當中，連網裝置通常以低電壓操作有較佳的能源效率表現也有較長的電池續航力，因此本論文之類比數位比較器設計在一個0.5伏與1伏雙供電之系統。低電壓循序漸近類比數位轉換器之轉換速率非常低，為了達到每秒取樣一億次的取樣速率，採用時間交錯式的系統架構。當中的子轉換器延續半休眠切換之概念，以求較低的電容切換功耗。本論文改良半休眠切換應用於時間交錯式架構，提出共用半休眠切換技術，透過重複使用閒置的子轉換器，降低所需之子轉換器總數。
本電路之原型晶片採用40奈米1P9M互補式金氧半導體製程製作，核心電路面積為600×870 μm2。在1.0/0.5 V供電以及每秒取樣1000萬次操作之下，本晶片可達到56.145 dB之訊號雜訊加失真比(SNDR)，對應等效解析度(ENOB)為9.03位元。其功耗為35 μW，換算能源效率指標(Walden figure-of-merit, FoMW)為9.36 fJ/conversion-step。在取樣頻率為每秒取樣1億次時，僅達到46.121 dB之SNDR，ENOB為7.369位元，其功耗為284 μW，能源效率指標FoM為17.28 fJ/conversion-step。

關鍵字

高速 ； 低電壓 ； 高能源效率 ； 時間交錯式 ； 連續漸進式類比數位轉換器

並列摘要

This thesis presents a 12-bit 100MS/s time-interleaved (TI) successive-approximation register (SAR) analog-to-digital converter (ADC) using shared semi-resting (SSR) switching technique.
For Internet-of-Things (IoT) applications, the connecting devices usually operate in low voltage supply for better energy efficiency and longer lifetime of batteries. Thus, the proposed ADC is designed in a dual supply system of 0.5 V and 1 V. The conversion rate of a low-voltage SAR ADC is slow. To achieve targeted 100MS/s sampling rate, the ADC adopts time-interleaved architecture. The sub-ADCs inherit the low capacitor switching power concept of the semi-resting (SR) switching technique. This thesis proposes the shared semi-resting (SSR) switching technique, which is a reformed SR technique used in TI architecture. The total required number of sub-ADCs is reduced by re-using idle sub-ADCs.
The prototype was fabricated in 40 nm 1P9M CMOS technology with a core area of 600×870 μm2. At 1.0/0.5 V supply voltage and 10 MS/s sampling rate, the ADC achieves SNDR 56.145 dB with corresponding ENOB 9.03-bit and consumes a power of 0.035 mW, resulting in a Walden figure-of-merit (FoMW) 6.69 fJ/conversion-step. At 100 MS/s sampling rate, the ADC achieves SNDR 46.121 dB with ENOB 7.369-bit and consumes a power of 284 μW, resulting FoMW 17.28 fJ/conversion-step.

並列關鍵字

high-speed ； low-voltage ； energy-efficient ； time-interleaved ； SAR ADC

參考文獻

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