使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器

論文提要內容：系統晶片會隨著製程、供應電壓定與溫度偏異而產生飄移，電路上會產生非理想的偏異，會造成系統上的不穩定，進而造成晶片的不正常工作，更嚴重而導致晶片的損壞，如何設計出一不隨製程、電壓與溫度變異且低功率消耗的穩壓器便是研究中一個重要的議題，在電路設計上使用數位電路才取代誤差放大器，因此，此論文目標為設計出一個使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器。低壓降線性穩壓器有幾項主要考量的特性參數: (1) 輸出電壓差(△V)與靜態電流(Quiescent Current, Iq) (2) 線性調節率(Line Regulation, LNR) (3)負載調節率(Load Regulation, LDR)；這些參數都與負載電流、精準度、穩壓時間有著密不可分的關係。整體電路可分為三大部分，第一部分為利用8位元連續漸近式類比數位轉換器架構，第二部分為功率電晶體的切換，而第三部分為比較器。低壓降線性穩壓器電路的設計，產生一電壓誤差10%的電壓與一最低與最高的可承受電流，而這兩電壓與電流經由功率電晶體後，最後輸出電壓還能穩定在固定的電壓，利用連續漸近式類比數位轉換器的訊號來控制功率電晶體以達到穩定的輸出電壓，並且降低在穩態中，所消耗的靜態電流。首先利用比較器來比較輸入電壓與原供應電壓的誤差來控制回授電阻的切換。第二利用電流的變化來切換回授電阻並控制功率電晶體的開或關。最後第三點，在設計連續漸近式類比數位轉換器架構和比較器部分，盡量降低DC電流消耗以節省整體的電流消耗。

關鍵字

低壓降線性穩壓器；連續漸近式；類比數位轉換器

並列摘要

Abstract: Soc circuit will produce a non-ideal effect with process, supply voltage, and temperature, which cause the chip does not work or lead to damage to the chip in serious. And how to design a low power consumption of the circuit is an important issue. We will design a circuit which use of the successive approximation analog to digital converter to replace error amplifier. Therefore, this paper the target for the design of a low dropout linear regulator with successive approximation analog to digital converter architecture. There are several key considerations of low dropout linear regulator characteristic parameters: (1) The output voltage difference (△ V) (2) linear regulator with quiescent current (The Quiescent Current, Iq) rate (Line Regulation, LNR) (3 ) load Regulation (Load Regulation, LDR); these parameters has a close relationship with the load current, precision, settling time. The circuit can be divided into three parts, the first part of the 8-bit successive approximation analog-to-digital converter architecture, the second part is the switching of the power transistor, the last part is the comparator. Using the signal from SAR ADC to control the power transistor to achieve the output voltage, and reduce the quiescent current in the steady state. First, compare the input voltage and the original supply voltage to control the feedback resistor switching. Second, current changes will control turn on the power transistor or turn off the power transistor. The simulation results are based on 0.18μm CMOS process. The current efficiency is 99.94%. Moreover, the quiescent current of the circuit is 15.8μA in a heavy load condition.

並列關鍵字

LDO ； SAR ； ADC

參考文獻

[1] Yat-Hei Lam and Wing-Hung Ki, “A 0.9V 0.35um adaptively biased CMOS LDO regulator with fast transient response,” IEEE International Solid-State Circuits Conference, pp. 442–626, Feb. 2008.

[2] Chunlei Shi, B. C. Walker, E. Zeisel, B. Hu and G. H. McAllister, “A highly integrated power management IC for advanced mobile applications,” IEEE Journal of Solid-State Circuits(JSSC), vol. 42, no. 8, pp. 1723–1731, Aug. 2007.

[3] Bin-Da Liu, Ying-Cheng Wu and Chun-Yueh Huang, ”A low dropout voltage regulator with programmable output,” IEEE Industrial Electronics and Applications (ICIEA), pp. 3357-3361, May 2009.

[4] Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po Hing Chen, Kazunori Watanbe, Makoto Takamiya, and Takayasu Sakurai, “0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65 nm CMOS,” IEEE Custom Integrated Circuit Conference(CICC), pp. 1-4, September 2010.

[5] Masafumi Onouchi, Kazuo Otsuga, Yasuto Igarashi, Toyohito Ikeya, Sadayuki Morita, Koichiro Ishibashi, and Kazumasa Yanagisawa, “A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process,” IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 37-40, November 2011.

國際替代計量

使用連續漸近式類比數位轉換器架構之低壓降線性穩壓器

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