Title

電場基礎模型與傳統熱載子壽命模型之比較

Translated Titles

Comparison of Hot-Carrier Lifetime Models Including a Novel One Based on Electrical Field

DOI

10.6841/NTUT.2011.00029

Authors

蔡岩峻

Key Words

通道熱載子 ; 電場 ; 溫度 ; 劣化 ; 壽命模型 ; Channel hot-carrier ; Field ; Temperature ; degradation ; Lifetime model

PublicationName

臺北科技大學機電整合研究所學位論文

Volume or Term/Year and Month of Publication

2011年

Academic Degree Category

碩士

Advisor

黃恆盛;陳雙源

Content Language

英文

Chinese Abstract

眾所週知,晶圓廠作MOSFET的通道熱載子(channel hot-carrier, CHC)可靠度測試時,都是在定電壓應力(constant voltage stress, CVS)的情況下,使元件特性提早劣化,並進一步評估其壽命,原因是為了縮短測試與評估元件良率的時間。而目前產業界,預測通道熱載子壽命則大多採用 1/V 模型來評估元件的壽命。 在本研究中,採用聯電65 nm製程,通道長度為是0.06 μm,寬度為10 μm,閘極氧化層為SiON,厚度為19.5 Å之nMOSFET作為實驗樣本,進行通道熱載子實驗。所有測試分別以25、50、85、100及125oC五個溫度進行。本研究也提出一個新的模型,考慮水平電場、垂直電場及溫度,提供電路CHC劣化與壽命的計算。經實驗後發現,在高溫及較高的CHC應力電壓下,元件劣化較為嚴重。而新的電場模型也成功地預測了元件的劣化情況,相較於傳統的1/V模型,擁有較佳的準確性。 本研究重要性在於能清楚告知晶圓廠或積體電路設計者,於操作電壓下不同通道長度的元件之壽命,並能更加準確地預測nMOSFET在CHC的劣化情形,這不僅可為產業縮短不少測試時間,更能提高預測的準確性及使用範圍。

English Abstract

It is well-known that channel hot-carrier (CHC) reliability test is executed with constant voltage stress (CVS) to investigate MOSFET degradation in wafer foundry. Furthermore, the device lifetime (τ) is thus determined. The industrial practice to estimate the device lifetime uses the lifetime model based on 1/V. The nMOSFETs being tested are fabricated by 65 nm process of United Micro-electronics Corporation (UMC). Their channel length is 0.06 μm, and channel width is 10 μm, gate insulator is SiON of 19.5 Å. For the CHC stress conditions, all tests were conducted at temperatures of 25, 50, 85, 100, and 125oC. A new electrical field related model, which includes the horizontal field, vertical field, and temperatures, is proposed to determine the degradation and lifetime of high temperature CHC effect. From the experimental results, the CHC stress with the maximal stress voltage and the highest temperature causes the most severe device degradation. Comparing with the traditional 1/V model, the new field related model can successfully predict device degradation. The significance of this study is to clearly give wafer foundries and IC design houses the device lifetime for different channel length and more accurately predicting the degradation. It is not only to reduce the tested time but also improve the accuracy and range of application in CHC reliability issue.

Topic Category 機電學院 > 機電整合研究所
工程學 > 電機工程
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