Title

應用於雙極性電晶體選擇器電阻式隨機存取記憶體之熱察覺感測電路

Translated Titles

A Thermal Aware Current Sensing Circuit for RRAM using BJT selector

Authors

郭家辰

Key Words

雙極性電晶體 ; 電阻式隨機存取記憶體 ; 熱察覺 ; 感測電路 ; BJT ; RRAM ; Thermal Aware ; Sense Amplifier

PublicationName

清華大學電機工程學系所學位論文

Volume or Term/Year and Month of Publication

2013年

Academic Degree Category

碩士

Advisor

張孟凡

Content Language

英文

Chinese Abstract

手持式消費性電子產品、智慧型車用電子等產品需要非揮發性記憶體做程式的儲存。而產品要達到高效能與快速回應的目標,對於執行程式將有高速讀取的需求。藉由非揮發性內嵌式記憶體與微控制單元(MCU)整合,可成功大大提高MCU之高速資料處理速度。 目前傳統的內嵌式記憶體都使用快閃記憶體,然而快閃記憶體(Flash memory)有讀取與寫入速度慢,寫入操作無法直接寫入(需要block erase),並需要高電壓。製程縮小至奈米等級之後,快閃記憶體在微縮上遇到了許多物理限制,使其成本上升或是特性劣化。因此開發新型態非揮發性記憶體是必需且迫切的。電阻式記憶體(RRAM)為公認相當具有潛力取代快閃記憶體,如給予適當的寫入驅動電流,其可達到快速直接寫入、低寫入電壓與低功耗、具有快速讀取度、寫入阻值均勻穩定並可在長時間儲存後擁有穩定而不漂移的阻值等優點。 電阻式記憶體目前面臨兩個主要的挑戰: 1. 滿足寫入驅動電流的要求並減小驅動電晶體的面積來提高密度 2. 加大讀取電流提高資料讀取良率與讀取速度的同時避免讀取干擾 在此篇論文中,我們使用了與CMOS製程相容的創新之寄生BJT元件,可節省4.5倍以上的面積。但BJT驅動能力對溫度具有較高的敏感度,若是以傳統箝制電路將位元線電壓固定,在高溫時即可能因溫度升高而造成讀取干擾的問題。而若是以預留邊限(margin)改變箝制電壓使傳統箝制電路在高溫時不會讀取干擾,則在低溫時讀取電流將下降並影響良率。 因此我們提出具溫度警覺位元線偏壓讀取機制(Temperature-Aware Bit-line Bias Scheme)來解決BJT溫度變異的問題。此機制在低溫下可提高4.7倍的細胞電流,配合具溫度警覺之加速機制可提高1.6倍的讀取速度。 我們分別以0.18微米與65奈米製程實作1Mb與2Mb的BJT RRAM記憶體測試晶片。量測結果其讀取速度可達到4.2ns and 4.7ns, 為目前全世界Mb等級RRAM晶片中最快的速度表現。

English Abstract

Handheld electronics, car electronics, and portable biomedical electronics require nonvolatile memory for code storage. In order to achieve high performance operation, fast program code access for microcontroller unit (MCU) is prerequisite. By integrating embedded memory with MCU, higher processing performance can be achieved. Flash memory is the mainstream embedded nonvolatile memory. However, Flash memory cannot achieve high speed write operation due to sequential write。It also requires high voltage (>10V) to perform write operation。Furthermore, it is difficult to scale down Flash in deep nanometer scale. Thus, the research and development of emerging nonvolatile memory is necessary and becoming popular topic. Among those emerging memories, Resistive Random Access Memory (RRAM) is one of the most promising candidates. It has attractive characteristics such as low write voltage, fast write speed, low write energy, and good retention time. However, two major challenge should be solved for RRAM: 1. Reducing the area of cell select switches, while satisfying write current requirements. 2. Maximizing ICELL for yield and speed, while maintaining a small voltage drop across the RRAM device (VR) to prevent read disturbance. In this work, a logic process compatible vertical parasitic BJT (VPBJT) is used to reduce the macro area. Comparing to CMOS array, the VPBJT can achieve 4.5X smaller macro area. However, BJT is sensitive to temperature variation which affects read reliability. We propose a thermal-aware bitline (BL) voltage bias scheme (TABB) for current-mode read with 4.7x larger cell current, and a 1.6x faster read speed. We fabricated 0.18μm 1Mb and 65nm 2Mb VPBJT RRAM macros to confirm the efficacy of the proposed sensing scheme. 4.2ns and 4.7ns access time have been measured for 0.18μm and 65nm macro respectively, which is the fastest random read speed among reported Mb-scaled NVM macros.

Topic Category 電機資訊學院 > 電機工程學系所
工程學 > 電機工程
Reference
  1. [1] L. Seokkiu, "Scaling Challenges in NAND Flash Device toward 10nm Technology," in Memory Workshop (IMW), 2012 4th IEEE International, 2012, pp. 1-4.
    連結:
  2. [4] S. K. Lai, "Floating gate memories: Moore's law continues," in VLSI Technology, 2005. (VLSI-TSA-Tech). 2005 IEEE VLSI-TSA International Symposium on, 2005, pp. 74-77.
    連結:
  3. [8] F. Irom, D. N. Nguyen, G. R. Allen, and S. A. Zajac, "Scaling Effects in Highly Scaled Commercial Nonvolatile Flash Memories," in Radiation Effects Data Workshop (REDW), 2012 IEEE, 2012, pp. 1-6.
    連結:
  4. [9] J.-P. Colinge and C. A. Colinge, Physics of Semiconductior Devices, 2002.
    連結:
  5. [10] R. Takemura, T. Kawahara, K. Miura, H. Yamamoto, J. Hayakawa, N. Matsuzaki, K. Ono, M. Yamanouchi, K. Ito, H. Takahashi, S. Ikeda, H. Hasegawa, H. Matsuoka, and H. Ohno, "A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1'/`0' Dual-Array Equalized Reference Scheme," Solid-State Circuits, IEEE Journal of, vol. 45, pp. 869-879, 2010.
    連結:
  6. [14] H. Yoda, S. Fujita, N. Shimomura, E. Kitagawa, K. Abe, K. Nomura, H. Noguchi, and J. Ito, "Progress of STT-MRAM technology and the effect on normally-off computing systems," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 11.3.1-11.3.4.
    連結:
  7. [15] H.-C. Yu, K.-C. Lin, K.-F. Lin, C.-Y. Huang, Y.-D. Chih, T.-C. Ong, J. Chang, S. Natarajan, and L. C. Tran, "Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 224-225.
    連結:
  8. [17] K. C. Chun, H. Zhao, J. D. Harms, T.-H. Kim, J.-P. Wang, and C. H. Kim, "A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory," Solid-State Circuits, IEEE Journal of, vol. 48, pp. 598-610, 2013.
    連結:
  9. [18] G. De Sandre, L. Bettini, A. Pirola, L. Marmonier, M. Pasotti, M. Borghi, P. Mattavelli, P. Zuliani, L. Scotti, G. Mastracchio, F. Bedeschi, R. Gastaldi, and R. Bez, "A 90nm 4Mb embedded phase-change memory with 1.2V 12ns read access time and 1MB/s write throughput," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 268-269.
    連結:
  10. [23] G. Servalli, "A 45nm generation Phase Change Memory technology," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
    連結:
  11. [25] H. Y. Cheng, T. H. Hsu, S. Raoux, J. Y. Wu, P. Y. Du, M. Breitwisch, Y. Zhu, E. K. Lai, E. Joseph, S. Mittal, R. Cheek, A. Schrott, S. C. Lai, H. L. Lung, and C. Lam, "A high performance phase change memory with fast switching speed and high temperature retention by engineering the GexSbyTez phase change material," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 3.4.1-3.4.4.
    連結:
  12. [26] J. Y. Wu, M. Breitwisch, S. Kim, T. H. Hsu, R. Cheek, P. Y. Du, J. Li, E. K. Lai, Y. Zhu, T. Y. Wang, H. Y. Cheng, A. Schrott, E. A. Joseph, R. Dasaka, S. Raoux, M. H. Lee, H. L. Lung, and C. Lam, "A low power phase change memory using thermally confined TaN/TiN bottom electrode," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 3.2.1-3.2.4.
    連結:
  13. [27] T. Morikawa, K. Akita, T. Ohyanagi, M. Kitamura, M. Kinoshita, M. Tai, and N. Takaura, "A low power phase change memory using low thermal conductive doped-Ge2Sb2Te5 with nano-crystalline structure," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 31.4.1-31.4.4.
    連結:
  14. [30] M. Qazi, M. Clinton, S. Bartling, and A. P. Chandrakasan, "A low-voltage 1Mb FeRAM in 0.13μm CMOS featuring time-to-digital sensing for expanded operating margin in scaled CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 208-210.
    連結:
  15. [31] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M. J. Tsai, "Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
    連結:
  16. [32] Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M. J. Tsai, "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
    連結:
  17. [34] Y. H. Tseng, C.-E. Huang, C. H. Kuo, Y. D. Chih, and C. J. Lin, "High density and ultra small cell size of Contact ReRAM (CR-RAM) in 90nm CMOS logic technology and circuits," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
    連結:
  18. [35] C. H. Cheng, A. Chin, and F. S. Yeh, "Novel Ultra-low power RRAM with good endurance and retention," in VLSI Technology (VLSIT), 2010 Symposium on, 2010, pp. 85-86.
    連結:
  19. [36] S. Shyh-Shyuan, C. Meng-Fan, L. Ku-Feng, W. Che-Wei, C. Yu-Sheng, C. Pi-Feng, K. Chia-Chen, Y. Yih-Shan, C. Pei-Chia, L. Wen-Pin, L. Che-He, L. Heng-Yuan, G. Pei-Yi, W. Sum-Min, F. T. Chen, S. Keng-Li, L. Chen-Hsin, C. Kuo-Hsing, W. Hsin-Tun, K. Tzu-Kun, K. Ming-Jer, and T. Ming-Jinn, "A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 200-202.
    連結:
  20. [39] M.-F. Chang, W. Che-Wei, C.-C. Kuo, S.-J. Shen, K.-F. Lin, S.-M. Yang, Y.-C. King, C.-J. Lin, and Y.-D. Chih, "A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 434-436.
    連結:
  21. [44] D. Ielmini, F. Nardi, and S. Balatti, "Evidence for Voltage-Driven Set/Reset Processes in Bipolar Switching RRAM," Electron Devices, IEEE Transactions on, vol. 59, pp. 2049-2056, 2012.
    連結:
  22. [45] D. Ielmini, "Modeling the Universal Set/Reset Characteristics of Bipolar RRAM by Field- and Temperature-Driven Filament Growth," Electron Devices, IEEE Transactions on, vol. 58, pp. 4309-4317, 2011.
    連結:
  23. [47] Y.-S. Chen, T.-Y. Wu, P.-J. Tzeng, P.-S. Chen, H.-Y. Lee, C.-H. Lin, and M.-J. Tsai, "Forming-free HfO2 bipolar RRAM device with improved endurance and high speed operation," in VLSI Technology, Systems, and Applications, 2009. VLSI-TSA '09. International Symposium on, 2009, pp. 37-38.
    連結:
  24. [48] T. Ninomiya, W. Zhigiang, S. Muraoka, R. Yasuhara, K. Katayama, and T. Takagi, "Conductive Filament Scaling of TaOx Bipolar ReRAM for Improving Data Retention Under Low Operation Current," Electron Devices, IEEE Transactions on, vol. 60, pp. 1384-1389, 2013.
    連結:
  25. [54] L. Chua, "Memristor-The missing circuit element," Circuit Theory, IEEE Transactions on, vol. 18, pp. 507-519, 1971.
    連結:
  26. [56] B. Gao, J. F. Kang, Y. S. Chen, F. F. Zhang, B. Chen, P. Huang, L. F. Liu, X. Y. Liu, Y. Y. Wang, X. A. Tran, Z. R. Wang, H. Y. Yu, and A. Chin, "Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching," in Electron Devices Meeting (IEDM), 2011 IEEE International, 2011, pp. 17.4.1-17.4.4.
    連結:
  27. [58] D.-j. Seong, J. Park, N. Lee, M. Hasan, S. Jung, H. Choi, J. Lee, M. Jo, W. Lee, S. Park, S. Kim, Y. H. Jang, Y. Lee, M. Sung, D. Kil, Y. Hwang, S. Chung, S. Hong, J. Roh, and H. Hwang, "Effect of oxygen migration and interface engineering on resistance switching behavior of reactive metal/polycrystalline Pr0.7Ca0.3MnO3 device for nonvolatile memory applications," in Electron Devices Meeting (IEDM), 2009 IEEE International, 2009, pp. 1-4.
    連結:
  28. [59] D. Ielmini, F. Nardi, and C. Cagli, "Universal Reset Characteristics of Unipolar and Bipolar Metal-Oxide RRAM," Electron Devices, IEEE Transactions on, vol. 58, pp. 3246-3253, 2011.
    連結:
  29. [61] H.-Y. Chen, S. Yu, B. Gao, P. Huang, J. Kang, and H. S. P. Wong, "HfOx based vertical resistive random access memory for cost-effective 3D cross-point architecture without cell selector," in Electron Devices Meeting (IEDM), 2012 IEEE International, 2012, pp. 20.7.1-20.7.4.
    連結:
  30. [62] H.-Y. Lee, Y.-S. Chen, P.-S. Chen, P.-Y. Gu, Y.-Y. Hsu, W.-H. Liu, W.-S. Chen, C. H. Tsai, F. Chen, C.-H. Lien, and M.-J. Tsai, "Comprehensively study of read disturb immunity and optimal read scheme for high speed HfOx based RRAM with a Ti layer," in VLSI Technology Systems and Applications (VLSI-TSA), 2010 International Symposium on, 2010, pp. 132-133.
    連結:
  31. [2] Y. Koh, "NAND Flash Scaling Beyond 20nm," in Memory Workshop, 2009. IMW '09. IEEE International, 2009, pp. 1-3.
  32. [3] K. Prall, "Scaling Non-Volatile Memory Below 30nm," in Non-Volatile Semiconductor Memory Workshop, 2007 22nd IEEE, 2007, pp. 5-10.
  33. [5] S.-P. Sim, K. S. Kim, H. K. Lee, J.-I. Han, W.-H. Kwon, J. H. Han, B.-Y. Lee, C. Jung, J. H. Park, D. J. Kim, D. H. Jang, W. H. Lee, C. Park, and K. Kim, "Fully 3-Dimensional NOR Flash Cell with Recessed Channel and Cylindrical Floating Gate - A Scaling Direction for 65nm and Beyond," in VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on, 2006, pp. 17-18.
  34. [6] http://www.itrs.net/ [Online].
  35. [7] Y. Shin, "Non-volatile memory technologies for beyond 2010," in VLSI Circuits, 2005. Digest of Technical Papers. 2005 Symposium on, 2005, pp. 156-159.
  36. [11] J. J. Nahas, T. W. Andre, B. Garni, C. Subramanian, H. Lin, S. M. Alam, K. Papworth, and W. L. Martino, "A 180 Kbit Embeddable MRAM Memory Module," Solid-State Circuits, IEEE Journal of, vol. 43, pp. 1826-1834, 2008.
  37. [12] D. Gogl, C. Arndt, J. C. Barwin, A. Bette, J. DeBrosse, E. Gow, H. Hoenigschmid, S. Lammers, M. Lamorey, L. Yu, T. Maffitt, K. Maloney, W. Obermaier, A. Sturm, H. Viehmann, D. Willmott, M. Wood, W. J. Gallagher, G. Mueller, and A. R. Sitaram, "A 16-Mb MRAM featuring bootstrapped write drivers," Solid-State Circuits, IEEE Journal of, vol. 40, pp. 902-908, 2005.
  38. [13] D. Halupka, S. Huda, W. Song, A. Sheikholeslami, K. Tsunoda, C. Yoshida, and M. Aoki, "Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 256-257.
  39. [16] M. Jefremow, T. Kern, W. Allers, C. Peters, J. Otterstedt, O. Bahlous, K. Hofmann, R. Allinger, S. Kassenetter, and D. Schmitt-Landsiedel, "Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 216-217.
  40. [19] K.-J. Lee, B.-H. Cho, W.-Y. Cho, S. Kang, B.-G. Choi, H.-R. Oh, C.-S. Lee, H.-J. Kim, J.-M. Park, Q. Wang, M.-H. Park, Y.-H. Ro, J.-Y. Choi, K.-S. Kim, Y.-R. Kim, I.-C. Shin, K.-W. Lim, H.-K. Cho, C.-H. Choi, W.-R. Chung, D.-E. Kim, K.-S. Yu, G.-T. Jeong, H.-S. Jeong, C.-K. Kwak, C.-H. Kim, and K. Kim, "A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput," in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 2007, pp. 472-616.
  41. [20] F. Bedeschi, R. Fackenthal, C. Resta, E. M. Donze, M. Jagasivamani, E. Buda, F. Pellizzer, D. Chow, A. Cabrini, G. M. A. Calvi, R. Faravelli, A. Fantini, G. Torelli, M. Duane, R. Gastaldi, and G. Casagrande, "A Multi-Level-Cell Bipolar-Selected Phase-Change Memory," in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, 2008, pp. 428-625.
  42. [21] F. Bedeschi, R. Fackenthal, C. Resta, E. M. Donze, M. Jagasivamani, E. C. Buda, F. Pellizzer, D. W. Chow, A. Cabrini, G. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi, and G. Casagrande, "A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage," Solid-State Circuits, IEEE Journal of, vol. 44, pp. 217-227, 2009.
  43. [22] H.-r. Oh, B.-h. Cho, W. Y. Cho, S. Kang, B.-g. Choi, H.-j. Kim, K.-s. Kim, D.-e. Kim, C.-k. Kwak, H.-g. Byun, G.-t. Jeong, H.-s. Jeong, and K. Kim, "Enhanced write performance of a 64-mb phase-change random access memory," Solid-State Circuits, IEEE Journal of, vol. 41, pp. 122-126, 2006.
  44. [24] C. Villa, D. Mills, G. Barkley, H. Giduturi, S. Schippers, and D. Vimercati, "A 45nm 1Gb 1.8V phase-change memory," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 270-271.
  45. [28] H. Shiga, D. Takashima, S. Shiratake, K. Hoya, T. Miyakawa, R. Ogiwara, R. Fukuda, R. Takizawa, K. Hatsuda, F. Matsuoka, Y. Nagadomi, D. Hashimoto, H. Nishimura, T. Hioka, S. Doumae, S. Shimizu, M. Kawano, T. Taguchi, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, Y. Kumura, Y. Shimojo, Y. Yamada, Y. Minami, S. Shuto, K. Yamakawa, S. Yamazaki, I. Kunishima, T. Hamamoto, A. Nitayama, and T. Furuyama, "A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes," in Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 464-465,465a.
  46. [29] D. Takashima, H. Shiga, D. Hashimoto, T. Miyakawa, S. Shiratake, K. Hoya, R. Ogiwara, R. Takizawa, S. Doumae, R. Fukuda, Y. Watanabe, S. Fujii, T. Ozaki, H. Kanaya, S. Shuto, K. Yamakawa, I. Kunishima, T. Hamamoto, and A. Nitayama, "A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 262-263.
  47. [33] S.-S. Sheu, P.-C. Chiang, W.-P. Lin, H.-Y. Lee, P.-S. Chen, Y.-S. Chen, T.-Y. Wu, F. T. Chen, K.-L. Su, M.-J. Kao, K.-H. Cheng, and M.-J. Tsai, "A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme," in VLSI Circuits, 2009 Symposium on, 2009, pp. 82-83.
  48. [37] R. Meyer, L. Schloss, J. Brewer, R. Lambertson, W. Kinney, J. Sanchez, and D. Rinerson, "Oxide dual-layer memory element for scalable non-volatile cross-point memory technology," in Non-Volatile Memory Technology Symposium, 2008. NVMTS 2008. 9th Annual, 2008, pp. 1-5.
  49. [38] W. Otsuka, K. Miyata, M. Kitagawa, K. Tsutsui, T. Tsushima, H. Yoshihara, T. Namise, Y. Terao, and K. Ogata, "A 4Mb conductive-bridge resistive memory with 2.3GB/s read-throughput and 216MB/s program-throughput," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2011 IEEE International, 2011, pp. 210-211.
  50. [40] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, "An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput," Solid-State Circuits, IEEE Journal of, vol. 48, pp. 178-185, 2013.
  51. [41] T.-Y. Liu, T. H. Yan, R. Scheuerlein, Y. Chen, J. K. Lee, G. Balakrishnan, G. Yee, H. Zhang, A. Yap, J. Ouyang, T. Sasaki, S. Addepalli, A. Al-Shamma, C. Chin-Yu, M. Gupta, G. Hilton, S. Joshi, A. Kathuria, V. Lai, D. Masiwal, M. Matsumoto, A. Nigam, A. Pai, J. Pakhale, C. H. Siau, X. Wu, R. Yin, L. Peng, J. Y. Kang, S. Huynh, H. Wang, N. Nagel, Y. Tanaka, M. Higashitani, T. Minvielle, C. Gorla, T. Tsukamoto, T. Yamaguchi, M. Okajima, T. Okamura, S. Takase, T. Hara, H. Inoue, L. Fasoli, M. Mofidi, R. Shrivastava, and K. Quader, "A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 210-211.
  52. [42] http://www.digikey.com/supply-chain-hq/us/en/articles/semiconductors/cellphone-exodus-will-deflate-nor-flash-market-again/1496 [Online].
  53. [43] A. Kawahara, K. Kawai, Y. Ikeda, Y. Katoh, R. Azuma, Y. Yoshimoto, K. Tanabe, W. Zhiqiang, T. Ninomiya, K. Katayama, R. Yasuhara, S. Muraoka, A. Himeno, N. Yoshikawa, H. Murase, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, "Filament scaling forming technique and level-verify-write scheme with endurance over 107 cycles in ReRAM," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International, 2013, pp. 220-221.
  54. [46] B. Gao, S. Yu, N. Xu, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu, and Y. Y. Wang, "Oxide-based RRAM switching mechanism: A new ion-transport-recombination model," in Electron Devices Meeting, 2008. IEDM 2008. IEEE International, 2008, pp. 1-4.
  55. [49] K. Aratani, K. Ohba, T. Mizuguchi, S. Yasuda, T. Shiimoto, T. Tsushima, T. Sone, K. Endo, A. Kouchiyama, S. Sasaki, A. Maesaka, N. Yamada, and H. Narisawa, "A Novel Resistance Memory with High Scalability and Nanosecond Switching," in Electron Devices Meeting, 2007. IEDM 2007. IEEE International, 2007, pp. 783-786.
  56. [50] S. R. Lee, Y.-B. Kim, M. Chang, K. M. Kim, C. B. Lee, J. H. Hur, G.-S. Park, D. Lee, M.-J. Lee, C.-J. Kim, U. I. Chung, I.-K. Yoo, and K. Kim, "Multi-level switching of triple-layered TaOx RRAM with excellent reliability for storage class memory," in VLSI Technology (VLSIT), 2012 Symposium on, 2012, pp. 71-72.
  57. [51] C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C.-J. Lin, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, "Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 29.6.1-29.6.4.
  58. [52] C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C. J. Lin, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, "Three-Dimensional 4F2 ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process," Electron Devices, IEEE Transactions on, vol. 58, pp. 2466-2472, 2011.
  59. [53] H. Y. Lee, Y. S. Chen, P. S. Chen, P. Y. Gu, Y. Y. Hsu, S. M. Wang, W. H. Liu, C. H. Tsai, S. S. Sheu, P. C. Chiang, W. P. Lin, C. H. Lin, W. S. Chen, F. T. Chen, C. H. Lien, and M. Tsai, "Evidence and solution of over-RESET problem for HfOX based resistive memory with sub-ns switching speed and high endurance," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.7.1-19.7.4.
  60. [55] S. T. Hsu, W. W. Zhuang, T. K. Li, W. Pan, A. Ignatiev, C. Papagianni, and N. J. Wu, "RRAM switching mechanism," in Non-Volatile Memory Technology Symposium, 2005, 2005, pp. 4 pp.-124.
  61. [57] G. Bersuker, D. C. Gilmer, D. Veksler, J. Yum, H. Park, S. Lian, L. Vandelli, A. Padovani, L. Larcher, K. McKenna, A. Shluger, V. Iglesias, M. Porti, M. Nafria, W. Taylor, P. D. Kirsch, and R. Jammy, "Metal oxide RRAM switching mechanism based on conductive filament microscopic properties," in Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 19.6.1-19.6.4.
  62. [60] Y.-B. Kim, S. R. Lee, D. Lee, C. B. Lee, M. Chang, J. H. Hur, M.-J. Lee, G.-S. Park, C.-J. Kim, U. i. Chung, I.-K. Yoo, and K. Kim, "Bi-layered RRAM with unlimited endurance and extremely uniform switching," in VLSI Technology (VLSIT), 2011 Symposium on, 2011, pp. 52-53.
  63. [63] A. S. Sedra and K. C. Smith, Microelectornic Circuits, 5th Edition, 2004.
  64. [64] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proceedings of the IEEE, vol. 91, pp. 489-502, 2003.
  65. [65] S. Dietrich, M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, and G. Mueller, "A Nonvolatile 2-Mbit CBRAM Memory Core Featuring Advanced Read and Program Control," Solid-State Circuits, IEEE Journal of, vol. 42, pp. 839-845, 2007.
  66. [66] C. J. Chevallier, C. H. Siau, S. F. Lim, S. R. Namala, M. Matsuoka, B. L. Bateman, and D. Rinerson, "A 0.13µm 64Mb multi-layered conductive metal-oxide memory " in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 260-261.
  67. [67] A. Kawahara, R. Azuma, Y. Ikeda, K. Kawai, Y. Katoh, K. Tanabe, T. Nakamura, Y. Sumimoto, N. Yamada, N. Nakai, S. Sakamoto, Y. Hayakawa, K. Tsuji, S. Yoneda, A. Himeno, K. Origasa, K. Shimakawa, T. Takagi, T. Mikawa, and K. Aono, "An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput," in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2012 IEEE International, 2012, pp. 432-434.