高解析中心式數位脈波寬度調變器設計

High resolution Centered Digital Pulse Width Modulator

傅錦憲(Jing – Hsien Fu)

指導教授 ： 陳怡然

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.02770

摘要

科技日新月異，全球電子商業隨著手機科技進步不斷蓬勃發展。現今通話的清晰度越來越要求，手機中的極發射器就需要更好的效能。因此極發射器中的E類功率放大器的控制電路「中心式數位脈波寬度調變器」漸漸需要提供高頻率、高精準度的脈波輸出。為了實現中心式數位脈波寬度調變器，本論文提出以相位產生電路先產生64組相位，再用相位組合電路組合出總共最多512種相位，最後經過邏輯閘產生PWM訊號。相位產生電路由延遲鎖定迴路與相分割電路(phase slicer circuit)作為基礎產生相位，相位組合電路由分段式複製延遲線、多工器和數位控制組成，以精準的產生所需要的脈波寬度並能抵抗製程、電壓、溫度變異。

本論文第一部分使用TSMC 90nm CMOS製程實作六位元中心式數位脈波寬度調變器，並具有相差180°雙相位輸出操作頻率為150MHz。最小脈波寬度為104ps且最後模擬結果為150MHz INL落在0.12 ~ -0.15 LSB之間，DNL落在0.16 ~ -0.1 LSB之間，FOM為1.15 pJ/bit。第二部分使用TSMC 90nm CMOS製程實作九位元中心式數位脈波寬度調變器，並具有相差180°雙相位輸出30MHz。最小脈波寬度¬為65ps且最後量測結果為30MHz INL落在±0.43 LSB之間，DNL落在±0.45 LSB之間，FOM為1.6 pJ/bit。

關鍵字

數位脈波寬度調變器 ； 延遲鎖定迴路 ； 分段式延遲線 ； CMOS

並列摘要

With the advance of science and technology, the significant developments on mobile phone applications lead the prosperous growth of grobal e-commerce. Since connection requires high quality nowadays, the transmitter in mobile system needs better performance. Centered digital pulse width modulator (Centered DPWM) that is applied to class E PA in polar transmitter of cell phone, needs to provide high frequency and high resolution output pulse gradually. This thesis presents a new centered DPWM architecture. First, this thsis proposes phase generation circuit, which can generate 64 + 8 phases. Then phase combination circuit combines all of these phases to generate 512 phases. PWM signal can be made flexible by these circuits’ co-operation. Phase generation circuit is composed of delay-locked loop (DLL) and phase slicer circuit (PS circuit). Phase combination circuit is composed of segmented replica delay line, MUX and digital control path.

The first part of this thesis proposed a 150MHz 6-bit centered DPWM using TSMC 90-nm CMOS process, and this circuit can generates centered pulse width modulation signal. The width per LSB of this circuit is 104ps. INL is 0.12 ~ -0.15 LSB, and DNL is 0.16 ~ -0.1 LSB in simulation. FOM is 1.15 pJ per bit. The second part of this thesis proposed a 30MHz 9-bit centered DPWM using TSMC 90-nm CMOS process, and this circuit can generates dual-phase pulse-width modulation signal. The width per LSB of this circuit is 65ps. INL is measured to be ±0.43 LSB. DNL is measured to be±0.45 LSB. FOM is 1.6 pJ per bit.

並列關鍵字

digital pulse width modulator ； delay-locked loop ； segmented delay line ； CMOS

參考文獻

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