電場基礎模型與傳統熱載子壽命模型之比較

蔡岩峻

doi:10.6841/NTUT.2011.00029

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電場基礎模型與傳統熱載子壽命模型之比較

Comparison of Hot-Carrier Lifetime Models Including a Novel One Based on Electrical Field

蔡岩峻 , Masters　　Advisor：黃恆盛;陳雙源　　

英文 DOI： 10.6841/NTUT.2011.00029

通道熱載子；電場；溫度；劣化；壽命模型； Channel hot-carrier ； Field ； Temperature ； degradation ； Lifetime model

Abstract │ Reference (22) │ Altmetrics

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Parallel Abstract 〈TOP〉

It is well-known that channel hot-carrier (CHC) reliability test is executed with constant voltage stress (CVS) to investigate MOSFET degradation in wafer foundry. Furthermore, the device lifetime (τ) is thus determined. The industrial practice to estimate the device lifetime uses the lifetime model based on 1/V.
The nMOSFETs being tested are fabricated by 65 nm process of United Micro-electronics Corporation (UMC). Their channel length is 0.06 μm, and channel width is 10 μm, gate insulator is SiON of 19.5 &Aring;. For the CHC stress conditions, all tests were conducted at temperatures of 25, 50, 85, 100, and 125oC. A new electrical field related model, which includes the horizontal field, vertical field, and temperatures, is proposed to determine the degradation and lifetime of high temperature CHC effect. From the experimental results, the CHC stress with the maximal stress voltage and the highest temperature causes the most severe device degradation. Comparing with the traditional 1/V model, the new field related model can successfully predict device degradation.
 The significance of this study is to clearly give wafer foundries and IC design houses the device lifetime for different channel length and more accurately predicting the degradation. It is not only to reduce the tested time but also improve the accuracy and range of application in CHC reliability issue.

Reference ( 22 ) 〈TOP〉

[1.1] C. H. Tu, S. Y. Chen, M. H. Lin, M. C. Wang, S. H. Wu, H. S. Huang, “The switch of the worst case on NBTI and hot-carrier reliability for 0.13 mm pMOSFETs,” Applied Surface Science, vol. 254, 2008, pp. 6186-6189.
連結：
[1.2] S. Y. Chen, C. H. Tu, J. C. Lin, P. W. Kao, W. C. Lin, Z. W. Jhou, S. Chou, J. Ko, and H. S. Haung, “Temperature effect on the hot-carrier induced degradation of pMOSFETs,” IIRW Final Report, 2006, pp. 163-166.
連結：
[1.3] J. C. Lin, S. Y. Chen, H. W. Chen, Z. W. Jhou, H. C. Lin, S. Chou, J. Ko, T. F. Lei, and H. S. Huang, “Investigation of DC hot-carrier degradation at elevated temperatures for n-channel metal-oxide-semiconductor field-effect-transistor of 0.13 µm technology,” Japanese Journal of Applied Physics, vol. 45, no. 4B, 2006, pp. 3144-3146.
連結：
[1.4] S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” IEEE International Reliability Physics Symposium, 2004, pp. 273-282.
連結：
[2.2] W. Shockley, “Problems related to p-n junctions in silicon,” Solid-State Electronics, vol. 2, 1961, pp. 35-67.
連結：

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