The thesis reports subthreshold analysis of PD SOI NMOS device considering floating body effect and drain-induecd barrier lowering. Chapter 1 gives a brief introduction about SOI CMOS devices and the scaling trends, including the comparison of the difference between the PD SOI and the FD SOI CMOS devices. Chapter 2 describes current conduction mechanism and equivalent circuit of the PD SOI NMOS device. The subthreshold analysis of the PD SOI NMOS device considering the various channel lengths has been performed. Chapter 3 discusses the PD SOI NMOS device in subthreshold region considering the back gate bias effect and various different carrier lifetimes. Chapter 4 is conclusion.