液晶顯示器驅動積體電路高壓元件之靜電保護研究

高壓元件於TFT液晶顯示器驅動IC中，扮演著可承受高電壓電流的重要角色，但元件製作程序和相關製程參數較一般低壓製程來得複雜許多，且在元件尺寸不斷微縮下，讓寄生元件導通和排放靜電放電能量的能力下降，再加上高壓元件常在嚴苛的環境下操作，讓發生閂鎖效應的機率增加，嚴重降低了高壓積體電路可靠性，有鑑於此，液晶驅動IC對靜電防護的可靠度議題一直受到高度重視。本論文中設計與製作了數種佈局參數的0.13 µm N型高壓元件（汲極橫向擴散金氧半電晶體），以傳輸線路脈衝產生系統（TLP）分析了元件在靜電放電發生時的行為、描述了元件在高電流導通時的電壓電流特性，同時以IC靜電測試儀器Zap Master MK2驗證HBM與MM的靜電等級，再利用故障分析技術探索ggNMOS（gate-ground NMOS）電路形式的靜電放電箝制元件之故障機制來研究改善，當高壓元件於Drain端contact下方佈植低壓N-Well的製程結構後，有效的使電場均勻分佈與分散電流密度，獲得了提升元件靜電等級的成果，據以找出ESD最佳化的尺寸與佈局規則，作為未來靜電放電高壓元件更深入研究與設計時的重要依據。

關鍵字

靜電放電；高壓元件

並列摘要

High voltage (HV) devices are important to thin-film-transistor (TFT) liquid crystal display (LCD) driver integrated circuits (IC) because they need to withstand high operation voltages and currents. However, HV ICs have much more complex fabrication processes than typical ICs. When miniaturization of ICs continues, some parasitic elements in HV ICs may be turned on and the endurance against electrostatic discharge (ESD) becomes weaker. In addition, HV devices are often operated in harsh environments, which can increase the probability of latch-up in the devices, severely reducing the reliability of the high voltage ICs. As a result, the ESD reliability of LCD driver ICs receives much attention in the semiconductor industry. In this study, we designed and fabricated 0.13 μm N-type HV lateral diffused (LD) metal oxide semiconductor (MOS) devices of different layouts. We used the transmission line pulse (TLP) generator system to analyze the performance of the devices under ESD conditions and to study the V-I characteristics of the devices in which high currents are turned on. The IC test equipment MK2 is used to verify the ESD level in the human body mode (HBM) and the machine mode (MM). Failure analysis was carried out to explore the failure mechanism for the gate-grounded NMOS (ggNMOS). When a low voltage (LV) N-Well is implemented in the Drain contact of LDMOS device, the ESD level is effectively upgraded. On the basis of the study, we have determined the optimal device scale and layout rules for the ESD protection, which are useful for future study and design for ESD elements of HV devices.

並列關鍵字

ESD ； High Voltage Device

參考文獻

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[13] Ming-Dou Ker, Senior Member, IEEE, and Kun-Hsien Lin, Member, IEEE, “The Impact of Low-Holding-Voltage Issue in High-Voltage CMOS Technology and the Design of Latchup-Free Power-Rail ESD Clamp Circuit for LCD Driver ICs ”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005

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[18] Ming-Dou Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. on Electron Devices, vol. 46, no.1 , pp. 173-183, Jan. 1999. (SCI, EI)

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液晶顯示器驅動積體電路高壓元件之靜電保護研究

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