The ever-growing capacity and continuously-dropping price have enabled the MLC SSDs to be widely adopted in the enterprises' storage subsystems. However, due to the NAND Flash's asymmetric read/write latency, the write performance is often the I/O bottleneck of the MLC SSD-based storage subsystems. Moreover, since many server I/O workloads are bursty, the storage subsystems may experience peak write request rates that are over an order of magnitude higher than average load. This requires significant overprovisioning for peaks in order to make the peak write latency meet the enterprises' internal SLOs (Service-Level Objectives) for their storage subsystems, such as the 99th percentile I/O latency < 100ms. The write heterogeneity (i.e. the MLC/SLC-mode write) in MLC SSDs provides great potential for the storage subsystems to improve the peak write latency, reducing the cost of massive overprovisioning for meeting the SLO's latency requirement. To minimize the lifetime impact of the SLC-mode writes, in this thesis, we propose a SLO-aware SSD Architecture which meets the SLO with minimal SLC-mode writes used. This architecture includes a novel algorithm to schedule both the issuing sequence and the SLC/MLC mode of each write request. Our scheduling algorithm can quickly find a local optimal schedule such that if there's no read and write requests in the future, all the write requests which have arrived in the SSD can meet the given targeted latency (e.g. 100ms) with minimal SLC-mode writes used. Unless there's no schedule which can meet the given targeted latency, our scheduling algorithm can always find this local optimum. To prevent the SSD from violating the SLO due to the read or write bursts in the future, this architecture adaptively adds a safety margin (e.g. 15ms) to the SLO's targeted latency value (e.g. 100ms), resulting in a smaller targeted latency value (e.g. 85ms) actually used for the scheduling algorithm. This makes the requests finish earlier, enabling the SSD to tolerate more read or write bursts in the future. To our knowledge, this is the first work targeted for the SLO by exploiting the write heterogeneity of the MLC NAND Flash. The experimental results show that with the help of our SLO-aware SSD Architecture, it's possible to meet the SLO without the need of overprovisioning more storage nodes. The 99th percentile I/O latency is significantly improved by up to 16x with only 2.9% lifetime impact in terms of the total erase count.