晶圓級晶片尺寸封裝熱疲勞壽命之電腦模擬分析

Computer Simulation of the Thermal Fatigue Life of WLCSP

夏育群(Yui-Chuin Shiah)

《科學與工程技術期刊》 3卷2期 (2007/06) Pp. 19-25

https://doi.org/10.7117/JSET.200706.0019

摘要

本文針對晶圓級晶片尺寸封裝在環境溫度循環負載下，利用有限元素分析軟體模擬熱與機械行為。理論根據Darveaux所提出之能量法利用黏塑性應變能密度為疲勞壽命預測之破壞判定依據，並藉此計算錫球的疲勞壽命與整體組件的可靠度。模型假設構裝體為全域建模，其數據皆為ANSYS模擬分析加速熱循環後所呈現。結果顯示各元件間熱膨脹係數的差異，為造成構裝體疲勞破壞的主要原因。就錫球部份而言，最大等效應力、應變皆發生在構裝體四周角落處，也是最容易造成疲勞破壞的地方。此外本模擬方法亦用以分析一特殊覆晶組件，其結果與實驗數據吻合。

關鍵字

晶圓級晶片尺寸封裝 ； 錫球可靠度 ； 有限元素分析

並列摘要

This study focuses on the reliability of a wafer-level chip-scale package (WLCSP) subjected to cyclic temperatures. Finite element analysis (FEA) is used to simulate the thermal condition and mechanical behavior. According to the theory of an energy-based law proposed by Darveaux, the analysis adopts viscoplastic-strain energy density as the basic criterion for calculating the fatigue life of the entire package, considered as its reliability. This package is analyzed by using the software program ANSYS, wherein a whole model simulates the applied thermal cycles. The results reveal that the fatigue failure is caused by a difference in the coefficient of thermal expansion (CTE) of the components. As such, the maximum equivalent stress and strain in solder bumps always occurs around a corner in the model, where the fatigue failure is initiated. Also, a similar analysis is implemented for a flip-chip sample. The veracity of the simulation is confirmed by a comparison with experiments reported by Solectron, an industrial company in the USA.

並列關鍵字

wafer-level chip-scale package WLCSP ； solder-joint reliability ； finite element analysis FEA