長除數頻率合成器的設計與分析

The Design and Analysis of Frequency Synthesizers with Large Multiplication Factors

李介文(Chieh-Wen Lee)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2012年)

https://doi.org/10.6342/NTU.2012.10101

摘要

無資料

關鍵字

鎖相迴路

並列摘要

In general, noise in PLLs can be sorted into two categories, reference noise and VCO noise. It is known that reference noise can be suppressed with a low bandwidth while VCO noise would be cleaned up more efficiently with a high bandwidth. Thus, it has a tradeoff in the choice of bandwidth. However, loop bandwidth should be kept below approximately one tenth of the reference frequency in practice to ensure the stability of the system. With some standard pre-defining the bandwidth mandatorily, it is hard to choose the loop bandwidth arbitrarily.
The situation is getting more serious when designing the frequency synthesizer with low reference frequency and large multiplication factors. For instance, when the PLL is applied into a control circuit in an LCD device, the input frequency is around 15 KHz ~ 100 KHz while the output frequency is almost around 30 MHz ~ 100 MHz. Therefore, limited by the reference frequency, the loop bandwidth in this application will be lower than 10 KHz, which make VCO noise hard to be suppressed. In this scenario, how to suppress the VCO noise efficiently becomes an important issue. Furthermore, low bandwidth will make loop filter capacitor too large to be integrated on-chip.
To overcome the problems mentioned above, this thesis proposes a hybrid frequency synthesizer based on a combination of PLL and multiplying DLL. It can achieve the best noise responses of key noise sources among all the proposed multi-loop architectures. Besides, a compact digital loop filter is utilized to save large area. However, with such a long reference period, it is hard for TDC to cover its full range. The limited tracking range of the P2D will result in long lock time. Therefore, we adopt a fast lock approach. By this approach, 4 bit TDC can be employed without sacrificing the setting time. Last not but least, we take the multiphase compensation method to suppress the quantization noise in high frequency offset.
This proposed hybrid frequency synthesizer operates from 350 MHz to 850 MHz with reference frequency equal to 32.768 KHz. It is fabricated in a 0.18μm CMOS technology with an core area of 1 x 0.7 mm2. The power consumption is 30 mW from 1.8-V power supply.

並列關鍵字

PLL

參考文獻

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