一個利用時間軸轉換技巧作後級放大的低功率導管式類比數位轉換器

A Low Power Pipelined ADC Using Time-Domain MDAC For Residue Amplification

張鈞維(Chun-Wei Chang)

指導教授 ： 陳信樹

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2013年)

https://doi.org/10.6342/NTU.2013.00684

摘要

本論文將介紹一個利用時間域後級電壓放大取代傳統轉導放大器放大的管線式類比數位轉換器。隨著先進製程對時脈精確度的提升，利用電流充電電容技巧將電壓訊號線性轉換成時脈訊號。此種技巧的實現只需使用到類比開關、電流源、電容以及閾值偵測比較器就可以達到電壓放大的效果。相較於傳統利用轉導放大器的形式，除了可以省面積外，又可以避免功耗較大的轉導放大器以及類比電壓驅動電路的設計，達到更為省電的目標。
此技巧驗證於65nm CMOS GP製成。根據模擬結果，操作在100MHz之取樣頻率，Nyquist之輸入頻率下，其訊號雜訊失真比為54.74dB，有效位元為8.8位元，總功耗為3.9mW。效能品質( FoM )為88 fJ/C.S，主動電路所佔之面積為0.09mm2。

關鍵字

管線式類比數位轉換器 ； 時間域

並列摘要

A pipelined ADC with time-domain MDAC, instead of using OTA topology, is presented. It takes advantage of the improved timing resolution in advanced CMOS technologies by transforming the voltage-domain signal into equivalent timing signal.
This technique simply uses analog switches, current sources, capacitors and threshold-detecting comparators. Compared to conventional OTA-based pipeline ADC, it occupies a small area, and achieves power efficiency by eliminating operational transconductance amplifier and avoiding design of power-hungry buffer for reference voltages.
This proof-of-concept prototype is demonstrated in a 65nm CMOS GP. According to Hspice simulation results, this prototype can operate at 100MHz. Signal-to-Noise and Distortion Ratio are 54.74dB when the input frequency is Nyquist rate, and the Effective Number of Bit is 8.8 bit. The total power consumption is 3.9mW. The figure of merit (FoM) is 88 f.J/C.S and its active area only occupies 0.09 mm2 .

並列關鍵字

Pipelined ADC ； Time-domain

參考文獻

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