應用於晶片間的9Gb/s電容耦合接收器

因為製程的演進，晶片內部的時脈也越來越快，但是晶片與晶片間的傳輸速度卻相對的進步緩慢。因此，設計出一個高速的傳送接收器變成一個重要的課題。本論文提出了一個高速且低功率損耗應用於晶片間傳輸的電容耦合式接收器，裡面包含了一個耦合電容，低擺幅脈衝接收器，以及一個限制放大器。在此種電路架構裡面，信號是以脈衝波的型式在傳輸線中傳送，透過電容值的選取，可以有效的控制脈衝波的振幅和長度，以降低ISI。脈衝波經由傳輸線傳遞後再由脈衝接受器解回NRZ信號，同時此脈衝接收器也具有低頻補償的功用。限制放大器使用改良型的Cherry-Hooper amplifier，它的功能則是放大從前級出來的信號，送至輸出端。經由模擬以及量測結果，此接收器可操作在9Gb/s，符合USB 3.0的規格 (4.8Gb/s)，此時的消耗功率為10.12mW，為一個高速低功耗的接收器。此電路是用TSMC 90nm CMOS製程來驗證此電路架構，晶片面積為430×255um^2。使用PRBS給資料，將資料經由10公分的FR4傳輸線來傳輸，量測結果顯示此接收器的最高工作速度可以操作在9Gb/s。

關鍵字

電容耦合接收器；限制放大器；晶片與晶片間傳輸；低擺幅脈衝接收器；互補式傳輸線

並列摘要

Because of technology scaling in CMOS chips, the internal clock frequency becomes faster and faster. However, the off-chip I/O signaling speed has been scaling much more slowly. To design high speed transceiver becomes an important issue. This thesis introduces a 9Gb/s AC coupled chip to chip receiver. This receiver includes coupling capacitors, a low swing pulse receiver, and a limiting amplifier. The function of the low swing pulse receiver is to receive pulse signal from the front stage and change the pulse signal into NRZ data. The amplitude of signal from pulse receiver is still too small, so we need to amplify it. In this thesis, a modified Cherry-Hooper amplifier is used as the main amplifier. By simulation and measurement, this receiver can operate in 9Gb/s and consumes only 10.12mW, which achieves the specification of USB 3.0 (4.8Gb/s). Comparing to other works, this receiver has higher operating speed (9Gb/s) and consumes less power (10.12mW). In conclusion, this chip is fabricated in TSMC 90nm CMOS technology. By measurement, this ac coupled receiver can be operated in 9Gb/s though 10cm FR4 microstripe line. The area of this chip is 430×255 um^2.

並列關鍵字

AC coupled interconnect (ACCI) ； receiver ； low swing pulse receiver ； low power ； high speed

參考文獻

[1] Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, and Paul D. Franzon, “3Gb/s AC Coupled Chip-to-Chip Communication Using a Low Swing Pulse Receiver”, IEEE JSSCC, VOL. 41, NO. 1, 2006

[2] T. Gabara andW. Fischer, “Capacitive coupling and quantized feedback applied to conventional CMOS technology,” IEEE J. Solid-State Circuits,vol. 32, no. 3, pp. 419–427, Mar. 1997.

[3] J. Kim, I. Verbauwhede, and M.-C. F. Chang, “A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1331–1340, Jun. 2005.

[4] S. E. Mick, J. M. Wilson, and P. D. Franzon, “4 Gbps high-density AC coupled interconnection,” in Proc. IEEE Custom Integr. Circuits Conf.,May 2002, pp. 133–140.

[5] S. A. Kuhn, M. B. Kleiner, R. Thewes, and W. Weber, “Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling,”in Proc. IEEE Int. Symp. Circuits Syst., vol. 1, Apr. 1995, pp.37–40.

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應用於晶片間的9Gb/s電容耦合接收器

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