壓控振盪器與製程漂移偵測設計

Voltage-Controlled Oscillators and Process Variation Monitors

謝易穎(Yi-Ying Hsieh)

指導教授 ： 盧奕璋

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01218

摘要

本篇論文我們使用CMOS的製程實現壓控振盪器，並且提出製程偵測的技巧，偵測振盪器的製程狀態。除了製程偵測的振盪器，本篇論文還設計了雙推式振盪器當做高頻訊號源使用，雙推式的架構能夠振盪高於電晶體的電流增益截止頻率，適合於設計高頻的振盪器。
第一個壓控振盪器使用0.18μm CMOS製程設計，電感我們採用外部磅線式，磅線有很高的品質因數且不佔晶片面積，缺點是電感值的漂移很大，為了偵測振盪器電晶體的製程，我們設計了製程偵測電路。量測結果壓控振盪器頻率涵蓋範圍600MHz，未使用製程偵測，電流全部打開的情況，晶片消耗4.2mW的功率，相位雜訊-108.56(dBc/Hz)@1MHz；使用製程偵測器後，功率消耗變為2.64mW，相位雜訊-106.31(dBc/Hz)@1MHz，增加了2(dBc/Hz)，但是功率消耗為原本的63%，同時振盪器的振盪頻率也是目前磅線設計中最快的。
接著我們修改偵測器的內部電路，使用90nm CMOS製程設計振盪器，因為0.18μm的設計採用三極管區偏壓的方式，消耗較大電流，90nm的設計使用飽和區偏壓方式，由製程偵測器調整尾端電晶體閘極端的偏壓。晶片設計採用內部電感方式，模擬結果振盪器能夠振盪在11GHz，有720MHz的振盪頻率範圍。在1MHz處，模擬出11GHz的相位雜訊為-104.5(dBc/Hz)，消耗功率大約1mW。
最後是高頻訊號源的設計，雙推式高頻訊號源使用90nm CMOS製程設計，使用交叉耦合式負電阻，給予0.9伏特的供應電壓。經過量測，實際的振盪頻率為111GHz，輸出振幅-23.1dBm，相位雜訊-95.8(dBc/Hz)@1MHz。

關鍵字

磅線 ； 壓控振盪器 ； 相位雜訊 ； 製程偵測器

並列摘要

In this thesis, three voltage-control-oscillators (VCOs) are designed. The first two VCOs equip process variation monitors to improve circuit performance. The other one is a push-push VCO that can operate faster than transistor unit current-gain frequency (ft).
The first work uses 0.18μm CMOS process. Since bond wire inductors have high quality factors without occupying much chip area, we use them to implement the VCO. A triode biased tail current transistor is used in this VCO. Since the triode biased transistor suffers from large process variations, a process variation monitor circuit is designed and implemented to solve the issue. This VCO has the tuning range of 600MHz. Without any calibration, VCO core power consumption is 4.2mW, and it has phase noise -108.56(dBc/Hz) at 1MHz offset. After calibrated by the process variation monitor, VCO core power consumption is 2.64mW and measured phase noise -106.31 dBc/Hz at 1MHz offset. Power consumption after calibration is reduced to 63% only, and this design has the highest output frequency among recently reported bond wire VCOs.
Then a new process variation monitor is designed using 90nm CMOS process. Since using triode biasing scheme usually needs more power, this 90nm CMOS VCO is biased in the saturation region instead. The gate bias of the tail current transistor is tuned by the process variation monitor. This design uses inner inductors and oscillates at 11GHz. From the simulation results, the tuning range of the oscillator is 720MHz, phase noise is -104.5 dBc/Hz at 1MHz offset, and the power consumption is 1mW.
Finally, the design of a cross-coupled push-push VCO in 90nm CMOS is presented. The supply voltage is 0.9V. The measurement result of the push-push port is 111GHz. Output power is -23.1dBm, and phase noise is -95.8(dBc/Hz) at 1MHz offset.

並列關鍵字

Bondwire ； voltage-controlled oscillator ； phase noise ； process variation monitor

參考文獻

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