第三代通用序列匯流排之功能性驗證環境設計及實作

Functional Verification Environment for Universal Serial Bus 3.0

王睿(Jui Wang)

指導教授 ： 郭斯彥

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.10292

摘要

今日積體電路設計的複雜度快速成長，使原本已經是電路設計流程中瓶頸的功能性驗證變得更加耗時，加上各種技術日新月異，新產品上市有時程上的限制，要在有限的時間內完成設計、驗證到下線生產的流程，對業界來說是不容小覷的議題。為了解決這個問題，一個有效率且完整的驗證環境占有非常重要的地位。
本論文設計並實作一個階層式，基於物件導向語言SystemVerilog的驗證環境，利用SystemVerilog中的Constrained-Random Stimulus Generation 功能，在有限的集合中隨機產生測試向量，以提高找到電路錯誤的機率，使驗證更加完整可靠；利用其物件導向的特性，提高程式碼重複使用率，不僅加速驗證程序、也簡化測試程式撰寫的複雜度；再配合語言內建機制強化驗證環境中功能性覆蓋率的計算，讓工程師能將有限的時間作更有效率的運用。
串列式匯流排(USB)是現今科技產業中廣泛使用的一種規格，舉凡各種產品皆可以此介面與電腦連接通訊。有鑑於此，本文以目前(西元2010年)最新的USB3.0規格為例，設計並實現一個具有前述各項優勢的驗證環境，希望可以對積體電路設計製造過程提供正面的助益，也提供一個相關應用領域可以互相參照與比較優缺的實例。

關鍵字

硬體驗證 ； 功能性驗證 ； 驗證環境 ； 通用序列匯流排

並列摘要

The complexity of digital electronic circuit is growing dramatically these years, making verification process, which is considered the major bottleneck, more challenging. Moreover, the rapid renew of various technologies is forcing IC industry to shorten the time-to-market of a product, which means to compress the time period of designing, verification, and tape-out process. To address this problem, an effective and comprehensive verification environment is necessary.
In this thesis, we design and implement a layered verification environment based on object oriented language, SystemVerilig. Utilizing the Constrained-Random Stimulus Generation property in SystemVerilig, the stimulus is generated randomly in a restricted subset, thus it not only raises the probability of hitting a bug but also makes programming task easier. The object oriented characteristic and built-in functional coverage mechanism makes this environment more efficient and reliable.
Universal Serial Bus is a commonly used interconnect interface, so we use it as an example to design and implement a verification environment. Hoping to offer some effort to IC industry and giving out an implementation for related studies to compare the pros and cons, we present this work.

並列關鍵字

Hardware Verification ； Functional Verification ； Verification Environment ； USB

參考文獻

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