在多加速器架構下藉由快取遞送消除輸入輸出記憶體管理單元的定址轉換

Eliminate IOMMU Address Translation for Accelerator-rich Architecture via Cache Forwarding

傅學俊(Hsueh-Chun Fu)

指導教授 ： 楊佳玲

國立臺灣大學/電機資訊學院/資訊網路與多媒體研究所/碩士(2017年)

https://doi.org/10.6342/NTU201703512

摘要

新興的多加速器架構由將傳統的處理器結合上許多不同的客製化加速器到同一個晶粒上。當越來越多的客製化加速起逐漸地被使用，一個統一的虛擬定址空間介於中央處理器單元與客製化加速器已經被提出來去減輕程序員的負擔。先前的研究引進了輸入輸出記憶體管理單元，使加速器能夠擁有統一的虛擬定址空間。然而，緩慢的輸入輸出記憶體管理單元無法達到有效率的頁表查詢，縮減了客製化加速器所帶來的優勢。此外，高關聯的輸入輸出轉譯後輩緩衝區在加速器的執行過程當中，消耗了無法被忽視的功率。相關研究提出了藉由卸載頁表查詢到中央處理器的記憶體管理單元的機制，來加速輸入輸出記憶體管理單元的定址轉換。然而，定址轉換仍然存在並且對整體效能及功率消耗造成一定程度的傷害。在我們的研究中，與其讓加速器藉由直接存取單元經過定址轉換去提取資料，我們提出了讓中央處理器的第一層快取主動地遞送資料到加速器的草稿記憶體。實驗評估中顯示了我們的機制分別對於基本架構以及相關研究的機制，達到14.8%以及8%的執行時間的改善，並且平均達到22.1%的功率節省。

關鍵字

異質計算 ； 多加速器架構 ； 虛擬記憶體系統

並列摘要

Emerging accelerator-rich architectures combine conventional processors with multiple customized accelerators onto the same die. Prior studies have introduced a IOMMU to enable the unified virtual address space for accelerators. However, the slow IOMMU is not capable of delivering efficient page walks and diminishes the gain of customized accelerators. Moreover, the highly-associative IOTLB can account for an unnegligible power consumption. Related work presents an offload page walker to speed up the IOMMU address
translation via utilizing the CPU’s MMU page walk cache. However, the IOMMU address translation still exists and harms the performance and the power. In this work, instead of letting DMA fetch data through the IOMMU address translation, we make the CPU’s L1 data cache directly forward the data to the accelerator’s scratchpad to avoid the IOMMU address translation. Evaluations show our proposed mechanism can achieve 14.8% and 8% improvements on execution time compared to the baseline and the state-of-the-art offload page walker and overall reach 22.1% power reduction on average.

並列關鍵字

Heterogeneous Computing ； Accelerator-rich Architecture ； Virtual Memory System

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