- 學位論文
利用高階合成之FPGA實時無損影像解壓縮加速器
Real-time lossless image decompression accelerator with High level synthesis on FPGA
摘要
數位微影相比於傳統微影製程，可以省下使用實體光罩的花費，轉而使用數位微鏡裝置(Digital Micromirror Device, DMD)進行曝光顯影之製程，用於印刷電路板及較不精細之半導體製程，而根據不同裝置的解析度，最大頻寬約20Gbps，而直接傳輸大量資料及處理是相當具有難度的。 此論文用 Run Length Encoding (RLE)來壓縮電路圖的二值圖檔，將壓縮資料傳至 Field Programmable Gate Array (FPGA)上做解壓縮，以此降低電腦端向外傳輸的頻寬，由於RLE是一種無損壓縮影像的方法，解壓縮後的圖必定會和原本的一致，不會因為壓縮而造成圖像失真。且RLE架構簡單，因此也對其進行改良來進一步提升壓縮率。 為了配合光機使用，因此需要在實時平台上來實作壓縮法，由於使用開發版上的ARM實作的成效與預期差距較大，因此轉而以FPGA硬體加速為目標，透過 High Level Synthesis (HLS)來做開發，可以快速且有效的試驗出較低資源使用及較高輸出量的設計，再以ARM來控制HLS的加速核，透過AXI 的傳輸介面，讓軟體端和硬體端相互配合，再將加速核算出的完整圖檔傳到數位微鏡裝置上做顯影。 以硬體加速後的頻寬，為實作在ARM上的12.25倍，相比於其他文獻，在以改良的RLE壓縮法和以電路圖為目標的條件下也相對優勢。
並列摘要
Digital lithography use Digital Micro-mirror Devices (DMDs) to replace the high-cost masks in the traditional lithography process, which could significantly reduce the cost of mask fabrication. However, the maximum bandwidth for controlling DMDs could approach 20 Gbps and could be a bottleneck for data transmission and processing. Run Length Encoding (RLE) is one of many lossless image compression methods that can avoid image aliasing after decompression. Moreover, RLE's architecture has the benefit of low complexity and can be easily modified for improved performance for a specific application. In this work, a modified RLE implementation was used to compress the binary images of printed circuit boards (PCBs) to reduce the amount of data that needs to be transmitted into the DMD device. Subsequently, the transmitted data was decompressed on an FPGA evaluation board the controls the DMD device. The decompression method needs to be implemented on a real-time platform. After a first round test, implementing RLE on an ARM processor would not meet the required performance of 20 Gbps. Therefore, hardware acceleration was utilized. High-level synthesis(HLS) was used to design a low-cost and high throughput core that can be implemented on an FPGA and controlled by an ARM processor with the AXI interface. The bandwidth after hardware acceleration is 12.25 times higher than the design implemented on an ARM processor. To our knowledge, the proposed and implemented modified RLE for PCB digital lithography applications was superior to other reported works.
參考文獻
延伸閱讀
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