本論文使用 TSMC 0.35 2P4M CMOS 製程,研製可以適用於CENCLEC BS EN 50065-1歐洲規範之電力線通訊系統接收機架構的類比基頻電路。電路設計上分成兩部份來實現,第一個部份是三階的柴比雪夫低通濾波器;而第二個部份為包含十三階巴特沃茲低通濾波器的電力線通訊系統接收機。 三階的柴比雪夫低通濾波器的設計上,採用蛙跳式濾波器架構,量測到的操作頻帶-3dB 頻率為 2.28MHz。片面積為1.086 x 0.947 mmxmm,消耗功率為8.413mW。電力線傳輸接收機中的十三階巴特沃茲低通濾波器採用傳統串接型設計,自動增益控制電路、等化器、峰值檢測器、及比較器皆在接收機系統設計內,整體晶片的消耗功率是21.21mW,晶片面積為1.914 x 1.853mmxmm。
This thesis presents the design and implements of the Power line communication receiver adapted to CENCLEC BS EN 50065-1 standard in TSMC 0.35 2P4M CMOS process. The main function, lowpass filter, is verified by two chips. One is the 3rd-order chebyshev LowPass filter. The filter type of the 3rd-order chebyshev LowPass filter is a leapfrog structure, and cascade method is applied to implement this high-order filter. According to measurement results, the gain level of the filter is 0dB. The f-3dB is 2.28MHz. The die area is 1.086 x 0.947 mm2 and the power consumption is 8.413mW. The other chip is designed for power line communication receiver which is comprised of an AGC circuit, a thirteenth-order Butterworth LowPass filter, an Equalizer, a peak detector, and a comparator. The f-3dB of the thirteenth-order Butterworth LowPass filter realized by Sallen-Key Biquad cascade is 125K Hz. The die area is 1.914 x 1.853 mm2 and the power consumption is 21.21mW.