適用於軟體定義無線電系統之低雜訊放大器的設計與製作

Design and Implementation of Low Noise Amplifier for SDR System

巫信賢(Hsin-Hsien Wu)

指導教授 ： 邱弘緯

國立臺北科技大學/電資學院/電子電腦與通訊產業研發碩士專班/碩士(2009年)

摘要

在此論文中，我們提出兩種適用於軟體定義無線電系統的低雜訊放大器。皆設計並實現於0.18μm互補式金屬氧化物半導體製程。第一種是具串聯電感隔離之並行雙頻帶低雜訊放大器。它能同時傳送窄頻帶增益並匹配在2.4GHz和5.8GHz。此低雜訊放大器的輸入匹配S11在2.4GHz和5.8GHz為-11.77dB及-20.87dB，輸出匹配S22為-8.29dB和-9.02dB，而隔離度S12則是-30.7dB和-31.61dB。也能達到15.86dB及15.28dB的小信號增益，4.42dB和4.83dB的雜訊指數，-15.5dBm和-19.5dBm的1dB壓縮點，以及-6dBm 和-7dBm的三階截止點。整個晶片的面積是1.39 × 1.4 mm2。
另外，第二種是具有寬頻雜訊抵銷技術之900MHz到3GHz的低雜訊放大器。透過使用電路設計的方法，能大大抑制匹配放大器的雜訊在我們需要的寬頻帶上。此晶片功率增益最高為15.52dB，900 MHz到3 GHz頻率間的增益平坦度約2dB，及3.03 dB到3.27 dB的雜訊指數。從1.8V供壓中消耗19.84mW的功率，並且只佔0.65 × 0.51 mm2的面積。
附錄部份則是介紹應用於射頻壓控振盪器的高品質因素可變電容之測試鍵，設計這個可變電容模型的重點在於能改變模型內部的長、寬來達到高的品質因素。當可變電容的品質因素上升，振盪器的相位雜訊就會下降。因此我們在此晶片上設計了八組的可變電容，測試在相同的電容值中，不同長、寬的品質因素之比較。

關鍵字

軟體定義無線電 ； 低雜訊放大器 ； 雜訊指數 ； 寬頻雜訊抵銷

並列摘要

In this thesis, we propose two kinds of the low noise amplifiers for software defined radio system. Designed and implemented in 0.18μm Complementary Metal Oxide Semiconductor process at the same time. The first kind is a concurrent dual band low noise amplifier implementation with a series inductive isolation. The low noise amplifier was transmitted narrow band gain simultaneously and matching at 2.4GHz and 5.8GHz. The low noise amplifier exhibits input matching with S11 of -11.77dB at 2.4GHz and -20.87dB at 5.8GHz, output matching with S22 of -8.29dB at 2.4GHz and -9.02dB at 5.8GHz, and isolation with S12 of -30.7dB at 2.4GHz and -31.61dB at 5.8GHz. It can also achieves small signal gain of 15.86dB and 15.28dB, noise figure of 4.42dB and 4.83dB, P1dB of -15.5dBm and -19.5dBm, and IIP3 of -6dBm and -7dBm.The over all chip area is 1.39 × 1.4 mm2.
In addition, the second kind is a low noise amplifier of 900MHz-3GHz which has a broadband noise cancelling technique. By using the circuit design method, the noise from the matching device is greatly suppressed over the desired broadband. The chip can achieves maximum power gain of 15.52dB, gain flatness of about 2dB among 900 MHz to 3 GHz. It consumes 19.84mW from a 1.8V supply and occupies an area of only 0.65 × 0.51 mm2.
The appendix introduces testkeys of high quality factor varactors for radio frequency voltage controlled oscillator's application. The purpose of designing the varactor is by changing L, W within models in order to get high quality factor. As quality factor of varactor rises, phase noise of voltage controlled oscillator will drop. So we have designed eight varactors on this chip to test the comparison of quality factor of different L, W in the same capacitance.

並列關鍵字

software defined radio ； low noise amplifiers ； noise figure ； broadband noise cancelling

參考文獻

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