新型相位估算硬式決策停止策略之渦輪解碼器設計

Turbo Decoder Design Employing New Phase Estimation Hard Decision Stop Criterion Method

張瑤璋(Yao-Chang Chang)

指導教授 ： 李文達

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2009年)

摘要

本論文提出一個以相位(Phase)為檢測基礎的高效率停止策略之渦輪碼解碼器積體電路設計。我們主要以HDA疊代終止演算法為核心，加以變化並輔以相位估算方法來減少疊代運算次數，以提高渦輪碼解碼器的效率。在高雜訊比的環境中，我們所提出的疊代終止演算法，比傳統的疊代終止演算法所需的疊代次數更少，最佳時更可達到只需一次的疊代次數，且資料錯誤更正率不低於傳統疊代終止演算法。在低雜訊比的環境中，我們所提出的演算法也可以判別資料是否已過度破損，超出渦輪碼解碼器的更正能力，並終止疊代以減少不必要的運算時間及功率消耗。
最後，我們將所提出之「新型相位估算硬式決策疊代終止演算法」渦輪碼解碼器，以TSMC 0.18μm 1P6M製程之Cell-based流程來完成晶片的實現。其晶片面積大小為1530μm x 1504μm，工作頻率為48MHz。

關鍵字

渦輪碼解碼器 ； 停止策略 ； 相位估算 ； 硬式決策

並列摘要

In this thesis, we proposed one high efficient stop criterion method for turbo decoder VLSI design with measurement in phase stage. The new stop criterion algorithm is based on Hard Decision Aided(HAD) stop criterion algorithm, and used phase estimation method to reduce iteration and thus improve turbo decoder latency efficiency. In high SNR environment, the iteration number of proposed algorithm is less than traditional stop criterion algorithm. Moreover, in best situation, our proposed algorithm needs only one iteration operation, and the error correction ability is almost the same with traditional algorithm. In low SNR environment, the proposed algorithm can detect the damage degree of received data whether it is out of the error correct ability of turbo decoder. And then it can stop iteration operation early to reduce operation time and power consumption.
Finally, this new phase estimation hard decision stop criterion turbo decoder has been designed with TSMC 0.18μm 1P6M process to accomplish. The decoder chip size is 1530μm x 1504μm, operation frequency is 48MHz.

並列關鍵字

Turbo decoder ； Stop criterion ； Phase estimation ； Hard decision

參考文獻

[1].C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo-codes,” IEEE International Conference on Communications, ICC '93, Geneva, vol. 2, 1993, pp. 1064 –1070.

[2].P. Robertson, E. Villebrun, and P. Hoeher, “A comparison of optimal and suboptimal MAP decoding algorithms operating in the log domain,” IEEE International Conference on Communications, ICC '95, Seattle, 1995, vol. 2, 1995,pp. 1009 –1013.

[3].A. Raghupathy and K. J. Ray Liu, “VLSI Implementation Considerations for Turbo Decoding using a Low Latency Log-MAP,” International Conference of Consumer Electronics, JJ, USA, pp. 182-183, June 1999.

[4].J. Hagenauer, “Iterative Decoding of Binary Block and Convoltional Codes,” IEEE Trans. On Information Theory, vol. 42, no.2, March 1996, pp. 429-445.

[5].B. Kim, H. S. Lee, “Reduction of the number of iterations in turbo decoding using extrinsic information,” Proceedings of the IEEE Region 10 Conference, TENCON 99, vol.1, pp.494-497, 1999.