高功率高效率之COMS功率放大器與時槽切換電路設計

High-Power and High-Efficiency CMOS Power Amplifier With Ramping Circuit

陳和銘(He-Ming Chen)

指導教授 ： 毛紹綱

國立臺北科技大學/機電學院/電腦與通訊研究所/碩士(2010年)

https://doi.org/10.6841/NTUT.2010.00427

摘要

近年來隨著可攜式無線通訊系統元件的市場快速成長，以CMOS製程降低晶片製作成本已成為一種未來的趨勢，但由於電晶體源極與汲極間的低崩潰電壓以及閘極氧化層的低崩潰電壓、高基板損耗，使得CMOS功率放大器效能受到很多製程特性的限制。
第一部分使先利用電晶體疊接(Cascode)架構以解決電晶體低崩潰電壓的缺點，並使用功率結合技術在晶片中實現阻抗轉換的功能，已達到大幅提升輸出功率和效率的目標，模擬結果顯示增益在1dB增益壓縮點為33dB，最大飽和輸出功率為33dBm，對應之功率附加效率為47.58%。
本論文另一重點為時槽切換電路的設計，使系統可藉由此電路以調整功率放大器中的控制電壓，使功率放大器輸出符合要求的各種輸出功率，以及快速時槽切換的功能。

關鍵字

CMOS ； 功率放大器 ； 時槽切換電路

並列摘要

During the past year in the fast growing market in wireless communication component industry, using CMOS process enhance lowering of manufacturing cost has become the future trend for companies, CMOS power amplifiers performance is limited because of its low breakdown voltage between source and drain as well as low gate-oxide breakdown voltage, and high substrate loss.
The first part using cascode structure to alleviate the breakdown voltage problem and employs power combining technique to achieve impedance transformation on chip for the purpose of increasing the output power and efficiency, Based on the simulation results,the PA delivers power gain of 33 dB of 1dB compression point, and maximum output power of 33dBm and an associated 47.58% power added efficiency (PAE).
Another focus of this thesis is to design a Vramping circuit, the ramping circuit sets the PA’s control voltage to the level necessary to produce the desired output power level and burst transmission.

並列關鍵字

CMOS ； Power Amplifier ； Ramping Circuit

參考文獻

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