動態部分可重組系統之內文儲存與恢復方法

Context Saving and Restoring Methodology for Dynamically Partially Reconfigurable Systems

賴麗文(Li-Wen Lai)

指導教授 ： 李宗演

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2007年)

摘要

動態部分可重組是將FPGA內部規劃成多個區塊，並使每個部分能個別作動態切換更新其內部電路。而動態可重組之硬體模組為了有內文切換(Context Switch)的能力，往往需使用大量的記憶單元來儲存內文。本論文提出一種新的硬體內文儲存與恢復方式，主要是減少儲存Readback時所需的訊框位址(Frame address)與計算暫存器位元索引(Bit Index)位置的資料量。我們分析FPGA結構的特性避免儲存重覆性的資料，以及在讀取訊框時利用其訊框位址的關連性，避免讀取多餘的訊框，達到節省資料的儲存量，減少讀取硬體內文的時間及複雜度。我們將此硬體內文儲存與恢復方法完全以硬體實現，並使用FPGA的SelectMAP介面控制Readback時的所有訊號，而以七段顯示計數器、多樣變化跑馬燈以及N位元除法器等的三種不同任務模組電路來驗證此方式的正確性，並計算所能節省的儲存空間及存取時間。而經由實驗結果證明，我們提出的儲存方式與相關研究比較下，我們的方法平均可以減少46.44％之儲存硬體內文的記憶體與減少4.011％之硬體模組重新配置的時間。

關鍵字

動態可重組系統 ； 回讀 ； 內文儲存與恢復 ； 現場可程式化邏輯閘陣列 ； SelectMAP介面

並列摘要

Dynamic partial reconfiguration is a scheme that divides the FPGA into different blocks and each block can be reconfigured individually. But dynamic reconfiguration hardware module also costs a lot of memory to save the content in context switching. Therefore, in this thesis, we propose a new the hardware context saving and restoring methodology. This method reduces the number of frame addresses and register bit indexes used for saving data location in operation of Readback. We utilize the relationship of frame addresses during reading frame to avoid reading the repeated frame addresses. Thus the method can reduce data storage space, time of reading hardware context and complexity. We implement proposed context saving and restoring by hardware. The operation of Readback is controlled by FPGA SelectMAP interface. We use three design examples, 7-segment display counter, LED control display and N-bit divider to verify the correctness of our proposed method and estimate the performance of storage and timing. Compared with related work, experimental results show that the proposed method can reduce average about 46.44% of memory used for saving hardware context and 4.011 % of time used for hardware reconfiguration.

並列關鍵字

Reconfigurable System ； Readback ； Context Saving and Reseoring ； FPGA ； SelectMAP Interface

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