基礎於掃瞄元件排序之方法以降低掃瞄試期間之功率消耗

Power Reduction for Scan Testing Based on Scan Cell Ordering 降低掃瞄試期間之功率消耗 Power Reduction for Scan Testing Based on Scan Cell Ordering

蔡嘉鴻(Chia-Hung Tsai)

指導教授 ： 曾王道

元智大學/資訊學院/資訊工程學系/碩士(2006年)

摘要

以掃瞄基礎的電路測試結構目前廣泛的被運用在電路設計上，然而面對測試過程當中，受測電路功率的消耗(Power consumption)卻被提升了，在測試過程當中，過度的功率消耗會造成產品成本的提高以及整體產能的下降。面對這個問題，我們提出了有效的解決方式。在本論文中，我們提出三階段的步驟解決我們的問題。首先定義出受測電路內，每個掃瞄元件(Scan cell)在測試向量(test vector)移動(shift)程序時對於受測電路所造成的影響程度。接下來我們對於每對掃瞄元件不同的排序方式，造成受測電路內部發生變化的程度，賦予不同的權重(weight)表示。最後建構有向的圖形，並加以搜尋，找出花費成本最小的路徑，藉以決定最後掃瞄元件的排列順序。此外，我們考量電路佈局(layout)的限制加到我們的排序程序當中。我們提出一個演算法，藉以在每次選擇一對掃瞄元件排序的過程中，不違反佈局限制的原則。以標準受測電路驗證我們提出的方式，實驗結果明顯的顯示在受測過程當中，功率的消耗降低，並比較其他未考量掃瞄元件對於受測電路內部影響程度的論文，所提出降低功率的方式，本論文所提出的方式有更好的實驗結果。

關鍵字

掃瞄元件/掃瞄串列 ； 功率消耗 ； 掃瞄元件重組

並列摘要

Scan-based circuit structure is widely used in circuit test design. The power consumption of a CUT (Circuit Under Test), however, arises during the test procedure. Excessive power consumption during test procedure may increase the cost of product and results in the decrease of overall yield. An effective solution is proposed in this thesis to overcome this problem by using a three-stage methodology. Firstly, we define the influence degree contributed by each scan cell in CUT when the test vector is shifting. Then we apply a weight for each pairs of scan cell according to transition degrees in different orders. In the third stage, a transition graph with directions is constructed and a search algorithm is applied to find the optima path, which has the lowest cost, to determine the orders of scan cells. In addition, layout constraints are also adopted as constrains in the search algorithm, thus it will not violate the layout rules in deciding the order of each pair of scan cells. We verified our proposed method via benchmark circuits, and the result shows obviously lower power consumption when comparing to the results of other papers that ignored influence degree of each scan cell under shifting.

並列關鍵字

Scan Cell/Scan Chain ； Power consumption ； Scan Cell Ordering

參考文獻

[1] Kaushik Roy, Rabindra K.Roy and Abhijit Chatterjee, “Stress Testing of Combinational VLSI Circuits Using Existing Test Set”, VLSI Technology, Systems, and Applications, June 1995,pp.93-98.

[2] P. Girard, C. Landrault, S. Pravossoudovitch and D.Severac , “Reducing Power Consumption during Test Application by Test Vector Ordering”, Proceedings of the IEEE International Symposium, Circuits and Systems ,1998,pp.296-299.

[3] P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, “A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation”, Proc. 9th Great Lakes Symp. VLSI, Mar. 1999, pp.24-27.

[4] X.Kavousianos, D.Bakalis, M.Bellos and D. Nikolos, “An Efficient Test Vector Ordering Method for Low Power Testing”, Proceedings. IEEE Computer society Annual Symposium,2004,pp.285-288.

[5] Y. Bonhomme, P. Girard, C. Landrault, and S. Pravossoudovitch, “Power Driven Chaining of Flip-flops in Scan Architectures”, Proc. of Int’l Test Conf., 2002, pp. 796-802.