記憶體IC靜電放電保護線路故障分析探討

A Case Study of Memory Device ESD (Electrostatic Discharge)Circuit Failure Analysis

鍾尤敏(Yu-Min Chung)

指導教授 ： 林秀麗

元智大學/工程學院/化學工程與材料科學學系/碩士(2007年)

摘要

因半導體製程線寬不斷的縮小，閘極氧化層因應變薄，使產品可靠度下降，環境中存在的靜電放電(Electrostatic Discharge, ESD)極易對IC(Integrated Circuit)造成損傷；本論文為研究某公司特定之SRAM產品其靜電放電保護線路之缺陷，並分析其於客戶應用端失效的原因；藉由栓鎖效應(Latch-up Effect) 及電性過度應力(Electrical Over Stress, EOS)的測試，成功的複製出與客戶端相同的失效現象，研判EOS應為造成IC損壞的原因；實驗中藉由液晶(Liquid Crystal)及發射式顯微鏡(Emission microscope)的分析進行IC異常熱點及亮點的定位，找出於EOS產生時該IC的電流匯集區域。
實驗發現此IC之ESD保護元件於7.2V時啟動並導致大電流的產生，使部份區域的金屬繞線因電流密度過大而燒壞；實驗中並取兩層光罩進行佈局(Layout)的修改，仍無法解決電流密度過大的問題，而基於成本的考量，光罩的改版即不再列入考慮；而藉由離子植入製程的移除，發現可將防止EOS損壞的能力提昇至10V以上，卻無法通過商用IC的ESD工業測試標準，進一步藉由離子植入濃度的調整，將EOS能力提昇至7.7V，且仍可通過ESD測試，調整後之製程參數將投入量產，預計可減少此產品於客戶應用端發生EOS造成失效的現象。
實驗中同時分析此產品於Layout設計的缺陷，建議將ESD保護線路於有限的空間中適當的分散，並能夠與相匹配的金屬線寬連接，提供日後設計者作為參考；而針對日後設計出操作電壓較高的產品，亦考量於量產前進行EOS的測試，以降低客戶於使用時發生EOS導致產品失效的情況。

關鍵字

靜電放電 ； 離子植入靜電放電防護

並列摘要

Device reliability is getting worse since the thickness of gate oxide is getting thinner, and the Integrated Circuits (ICs) are much more easily to be damaged comparing with the devices fabricated before. This thesis is to investigate a SRAM (Static Random Access Memory) product which returning from customer for failure analysis and was suspected to have weakness in circuit designing. By applying Latch-up and Electrical Over stress (EOS) tests, the failure phenomena in customer site can be duplicated successfully, and the EOS event is considered the root cause of device failure. Liquid Crystal (LC) and Emission Microscope (EMMI) were used to localize the current surge location in this investigation.
It is found that the ESD protection circuit turns on at 7.2V, which results in a large current and burns the metal line due to its current density was too high. Two methods were used to improve the EOS tolerance. The first method is mask changing to modify the layout and create another path for current discharging. The result was not as what was expected, and the layout modification was not taken into consideration since there is space limitation. The second method is ESD protection circuit implantation dosage modification. The EOS tolerance can be improved to 10V by removing the implantation process, but the ESD immunity was degraded and could not pass 2000V test which is the requirement for commercial grade ICs. Finally by decreasing the implantation dosage to 50% of the origin, the EOS tolerance can be improved to 7.7V and also can pass the commercial grade ESD test specification. The modified factor has been put into production, and the EOS induced failure is supposed to reduce in customer site in the future.
In this thesis, the weakness of the circuitry design of a SRAM product is studied. Appropriated separating the ESD protection circuits in a limited area is recommended to the designer and the width of the metal interconnect should also be considered. According to the high power ICs, applying EOS test on new design product is considered to include before mass production.

並列關鍵字

ESD ； ESD implantation

參考文獻

[1] Joachim C. Reiner, Thomas Keller, Hans Jaggi, Silvio Mira, “Impact of ESD-induced soft drain junction damage on CMOS product lifetime”, IEEE, Proceedings of 8th IPFA, Singapore, 77-78, 2001.

[2]Steven H. Voldman, “Electrostatic Discharge (ESD) and Failure Analysis: Models, Methodologies and Mechanisms”, IEEE, Proceedings of 9th IPFA, Singapore, 65-69, 2002.

[4] Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM), EIA/ JESD22-A115-A, Electronic Industries Association.

[7] Min Chul Jung, Sang Joon Hawng, Man Young Sung, Ey Goo Kang, “ESD Protection Circuit with an Improved ESD Capability for Input or Output Circuit Protection”, IEEE Journal of Circuits and Systems, Vol. 1, 468 ~ 471, 2005.

[11] Ming-Dou Ker, “Whole-Chip ESD Protection Design with Efficient VDD-to-VSS ESD Clamp Circuits for Submicron CMOS VLSI”, IEEE Transactions on Electron Devices, Vol. 46, No. 1, Jan. 1999.