多通道時間交錯式類比數位轉換器

Multi-channel Time-interleaved Analog-to-Digital Converter

王逸宏(Wang, Yi Hung)

指導教授 ： 朱大舜

國立清華大學/電機資訊學院/電機工程學系/碩士(2015年)

https://doi.org/10.6843/NTHU.2015.00402

摘要

類比數位轉換器是類比訊號與數位訊號的主要媒介，因此類比數位轉換器的效能大大影響了訊號接收端的品質，然而隨著資料傳遞量以及速度等需求的增長，高取樣速率高解析度的類比數位轉換器對於整體訊號接收端的解析度影響是漸趨重要的。

目前積體化資料皆以數位的形式運算，以類比的型態呈現，因此類比數位轉換器在系統晶片中扮演著一個重要角色。類比訊號由天線接收端進入系統中，由前端之低雜訊放大器先做預先的放大，將放大後的訊號經過降頻後藉由類比數位轉換器轉換至數位訊號，再將此訊號提供後端數位訊號處理做資料的運算，故類比數位轉換器之轉換效率以及效能對於整個訊號路徑俱有非常重要的影響，且類比數位轉換的過程中，常常遇到元件不理想、時脈的抖動與雜訊等問題，因此如何克服這些困難以產生正確的輸出訊號以提供後方數位訊號處理電路進行運算算是類比數位轉換器成功的關鍵。
隨著科技的進步，類比數位轉換器不斷在速度與解析度上做改進，從快閃式類比數位轉換器、管線式類比數位轉換器與連續漸進式類比數位轉換器，如圖二所示，其每種架構之類比數位器皆具有各自的取向，

本論文主要介紹多通道時間交錯式類比數位轉換器的研究，其中包含了多通道所造成的非理想效應分析、多通道時間交錯式取樣開關模擬結果，而後端類比數位轉換器分為連續漸進式類比數位轉換器以及導管式類比數位轉換器兩個部分介紹，連續漸進式類比數位轉換器為10位元每秒取樣100百萬次有效位元為9.92，DNL與INL為完美結果，平均消耗功率為2.42mW，每次轉換所消耗的平均能量為25fJ，導管式類比數位轉換器電路架構主要由快閃式類比數位轉換器以及切換電容式電路為基底的倍乘式數位類比轉換器所組成

關鍵字

類比數位轉換器 ； 多通道時間交錯技術

並列摘要

Analog-to-digital converter is the major intermedium of analog signals and digital signals, so the efficiency of analog-to-digital converter greatly affect the quality of the signal at the receiving end. However, with the rapid growth of data transfer volume and speed requirements, high sampling rate high-resolution analog digital converter for the impact on the resolution of overall signal receiving end is becoming much more crucial.

In the thesis, the researches of multi-channel time-interleaved analog-to-digital converter are mainly mentioned which includes the non-ideal effects analysis of multi-channel and simulation results of multi-channel time-interleaved sampling switches. The back-end analog-to-digital converter will be introduced and divided into two parts which is successive approximation analog to digital converter and pipeline analog to digital converter discretely. A 10-bit 100MS/s SAR ADC with ENOB 9.92 and perfect DNL、INL. The average power consumption is 2.42mW and the average energy consumption is 25fJ each conversion. The circuit structure of pipeline analog to digital converter is mainly comprised of Flash ADC and switch-cap sub-DAC

參考文獻

[1] S.Hashemi and B.Razavi, “A 10-Bit 1-GS/s CMOS ADC with FOM=70 fJ/Conversion,” IEEE CICC, Sep. 2012.

[3] M. Anthony et al., “A process-scalable low-power charge-domain 13-bit pipeline ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun.2008, pp. 222–223.

[4] W. FREY, “Bucket-brigade device with improved charge transfer”, IET Electronics Letters, Vol.9, No.25, pp.588–589, 1973.

[5] I. Ahmed, J. Mulder, and D. A. Johns, “A low-power capacitive charge pump based pipelined ADC,” IEEE J. Solid-State Circuits, vol. 45, no.5, pp. 1016–1027, May 2010.

[6] D. W. Cline and P. R. Gray, “A power optimized 13-b 5 M Samples/s pipelined analog-to-digital converter in 1.2um CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 294–303, Mar. 1996.