先進金氧半電晶體之界面與邊緣缺陷分佈量測及可靠度分析研究

Detection of interface and bulk trap distribution and reliability analysis for advanced MOSFET devices

呂君章(Lu, Chun Chang)

指導教授 ： 張廖貴術

國立清華大學/原子科學院/工程與系統科學系/博士(2014年)

摘要

隨著半導體工業接近傳統矽互補式金屬氧化物半導體(CMOS)的微縮極限，在未來引入新材料和創新的元件結構已是必然趨勢。高介電係數(high-k)材料已被提出，以取代傳統的二氧化矽作為金氧半元件的閘極介電層。高遷移率的材料也被認為將取代矽通道以實現更高的驅動電流和開關速度。鍺作為通道材料特別引起廣大的興趣，因為其具有較高的電洞和電子遷移率。然而，其界面特性和延伸的電荷捕捉問題已經被提出會嚴重地影響高介電係數金氧半元件的電特性。因此，提供一個準確和快速的測量界面陷阱密度和邊緣陷阱分佈的方法被認為是一個值得研究的課題。在本文中提出了數個基於電荷汲引(charge pumping)原理的缺陷量測技術，並針對測量結果作深入的探討。結合動態汲極偏壓的改良式變頻電荷汲引技術在本文中被提出，並用以量測在高介電係數電晶體缺陷的空間分佈。由通道熱載子電應力以及定電壓電應力所引致的缺陷增生亦在本文中被比較和討論。
在另一個研究主題中，一個不中斷電荷汲引量測(SSCP)技術被提出，並在不中斷電應力的情況下來量測電應力所引致的缺陷增生。實驗結果顯示SSCP在不中斷電應力所量測到的缺陷增生明顯的比傳統方法要高許多。此差異是由於傳統方法在量測時中斷電應力所造成的回復現象所導致。不同頻率電應力下所引致的臨界電壓飄移及界面缺陷增生也一起被量測討論；兩者都只與總累積的電應力時間有關，而與脈衝波的頻率和關閉時間無關。
在最後的研究中，ZrO2與HfON為介電層的p型電晶體元件，其界面缺陷密度、邊緣缺陷密度和電應力引致的缺陷增生被量測並比較。實驗結果顯示，ZrO2元件和HfON元件相比，具有較高的界面陷阱密度，但較低的邊緣陷阱密度；這意味著ZrO2元件具有較差的Ge/dielectric界面，但高品質的介電層特性。相較於HfON元件，ZrO2元件的可靠性提高可以歸因於其高品質的介電層擁有較低的原生邊緣陷阱密度，因此大大的抑制在介電層中陷阱的電荷捕捉行為。

關鍵字

電荷汲引 ； 界面缺陷 ； 通道熱載子 ； 缺陷分佈 ； 可靠度

並列摘要

As the semiconductor industry approaches the limits of traditional silicon complementary metal-oxide-semiconductor (CMOS) scaling, introduction of novel materials and innovative device structures has become necessary for the future of CMOS. High dielectric constant (high-k) material has been proposed to replace the conventional silicon dioxide as gate dielectrics of MOS devices. High mobility materials are also being considered to replace Si in the channel to achieve higher drive currents and switching speeds. Ge has particularly become of great interest as a channel material, owing to its high bulk hole and electron mobilities. However, the characteristic and extent of charge trapping in the interfacial layer between gate dielectric and silicon have been reported to affect strongly the electrical characteristics of high-k gated MOS devices. Hence, providing an accurate and quick measurement for density and distribution of interface and bulk traps is believed to be a valuable research topic. This work proposes several measurement techniques based on the principle of charge pumping (CP) and provides some discussion in depth for measurement results. A modified CP technique with dynamic drain bias and various gate pulse frequencies is proposed to characterize the distribution profiles of trap generation induced by channel-hot-carrier stress in MOSFETs with high-k gate stack. With dynamic drain biases, the drain depletion region during accumulation can be modulated. Hence, the trap distribution with respect to both dielectric depth and channel location can be characterized as well. The trap generation caused by channel-hot-carrier and constant voltage stresses is also compared. Results indicate that the generation of border trap induced by CVS is small and random distributed though whole channel, while that induced by CHC stress is large and localized around the gate-edge region inside the high-k dielectric.
In another study, a stress-and-sense charge pumping (SSCP) technique is proposed to measure the stress induced interface trap (ΔNit) in real time evolution without stress interruption. Results show that the ΔNit measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The ΔNit measured by SSCP method after interruption is approximately equal to that by the conventional one. The stress induced threshold voltage shift (ΔVth) and ΔNit under varies stress frequencies and duty cycles are also measured. The ΔVth seems to depend on the total stress time of stress pulse only. The ΔNit measured by SSCP with different frequencies and duty cycles are similar. The ΔNit also depends on the total stress time of stress pulse, but not the off time during the non-stress half cycle.
In the last study, the interface trap density, bulk trap density and stress induced trap generation of Ge-pMOSFETs with ZrO2 and HfON dielectrics are extracted and compared by CP technique with short transition time and various frequencies. Results show that ZrO2 device has higher interface trap density but lower bulk trap density than HfON device, which implies that ZrO2 device has inferior Ge/dielectric interface but high quality dielectric bulk. The improved reliability characteristics in ZrO2 device can be attributed to the low preexisting bulk trap density which greatly suppress charge trapping in the dielectric bulk.

並列關鍵字

charge-pumping ； interface trap ； channel-hot-carrier ； trap profile ； reliability

參考文獻

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