整合扇出晶圓級晶片尺寸封裝之小間距焊接墊高效率探針測試策略

隨著對於進階半導體產品在大規模整合，以及更小的單位元件有著不斷增加的需求，尤其在整合動態隨機存取記憶體 (DRAM) 及邏輯晶片，三維積體電路 (3D IC) 以及晶圓級晶片尺寸封裝 (WLCSP) 被認為是較有希望的方法。在整合扇出晶圓級晶片尺寸封裝 (InFO WLCSP) 中，大量的小間距焊接墊 (fine-pitch pads) 被用來做為晶片之間的連接介面，然而，由於焊接墊之間的間距不足，會導致周圍的焊接墊無法被同時用探針探測。如果小間距焊接墊無法被探測，那在焊接墊以及邊界掃描單元 (BSCs) 之間的連接便無法進行測試，這會造成更高的缺陷等級 (defect level)。根據產業上的調查，這些無法進行探測的小間距焊接墊會造成約1-2%的測試覆蓋率損失。為了增加整體的測試覆蓋率，我們提出了一個對於整合扇出晶圓級晶片尺寸封裝小間距焊接墊的鍵合前 (pre-bond) 測試方法。藉由我們提出的探針測試方法，在小間距焊接墊及邊界掃描單元之間的短路/斷路錯誤皆能夠被電子測試設備 (ATE) 測試。此外，對於只發生在周邊焊接墊的短路，我們另外提出了一個分組方法來決定在每個不同測試階段的測試資料 (test pattern) ，藉此來最小化測試時間。最後，我們也提出了數學證明來驗證我們的方法在不同的情況下可以達到100%的短路/斷路測試覆蓋率。

關鍵字

三維積體電路；探針測試

並列摘要

With the increasing demand of super high scale of integration and small form factor in advanced semiconductor products, especially those that integrate DRAM and logic dies, 3D IC and Wafer-Level Chip-Scale Packaging (WLCSP) are considered promising approaches. In Integrated Fan-Out (InFO) WLCSP, a large number of fine-pitch pads, where neighboring pads cannot be probed simultaneously due to insufficient pitch, are used as the contact interfaces of inter-die interconnections. If the fine-pitch pads cannot be probed, the interconnections between the pads and boundary scan cells (BSCs) cannot be tested, which can lead to higher defect level. From industrial investigation, untested fine-pitch pads lead to 1-2% test coverage loss. To improve the overall test coverage, we propose a pre-bond probing methodology for fine-pitch pads of InFO WLCSP. By the proposed probing schemes, open/short faults on the interconnects between the fine-pitch pads and BSCs can be all tested by the ATE. Moreover, for short faults that only occur between adjacent pads (interconnects), we propose a grouping method to determine the test patterns at each probing stage, which can minimize the test time. We also show that our method can achieve 100% test coverage of open/short faults.

並列關鍵字

3D IC ； 2.5D IC ； wafer test ； InFO WLCSP ； wafer probing ； interconnect test ； pre-bond test

參考文獻

[1] D. Yu, “A New Integration Technology Platform: Integrated Fan-Out Wafer-Level-Packaging for Mobile Applications,” in Proc. IEEE VLSI Technology Symposium, T46-T47, Jun. 2015.

[2] H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Wafer Level Chip Scale Package copper pillar probing,” Test Conference (ITC), 2014.

[3] C.C. Liu, S.-M. Chen, F.-W. Kuo, H.-N. Chen, E.-H. Yeh, C.-C. Hsieh, L.-H. Huang, M.-Y. Chiu, J. Yeh, T.-S. Lin, T.-J. Yeh, S.-Y. Hou, J.-P. Hung, J.-C. Lin, C.-P. Jou, C.-T. Wang, S.-P. Jeng, and D.C.H. Yu, “High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration,” Electron Devices Meeting (IEDM), 2012.

[4] C.-C. Chi, E.J. Marinissen, S.K. Goel, and C.-W. Wu, “Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base,” Test Conference (ITC), 2011.

[5] Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, C.-W. Wu, “A built-in self-test scheme for the post-bond test of TSVs in 3D ICs,” VLSI Test Symposium (VTS), 2011.

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整合扇出晶圓級晶片尺寸封裝之小間距焊接墊高效率探針測試策略

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