考量現代晶片封裝技術共同設計下之電源供應走線與微凸塊擺放設計流程

A Design Flow for Power Stripes and Micro Bumps Planning on Modern Chip-Package Co-Design

黃茗榆(Ming-Yu Huang)

指導教授 ： 陳宏明

國立交通大學/電機學院/電子工程系所/碩士(2020年)

摘要

在先進覆晶封裝技術流程中，電源供應走線和微凸塊是傳送訊號和保護電源完整性以達成垂直連接基板和晶片的關鍵。晶片在不同的設計下，通常會跟著相對應的設計進行最好的設計規劃微凸塊及電源供應走線方式，通常這一步驟會在產生訊號及電源訊號的傳輸路徑上耗費許多人力及時間成本。因此，我們提出兩個方法，其方法可以自動化地在晶片的高層金屬走線產生電源供應網路，與自動化設定微凸塊的座標位置。並根據晶片設計和製程封裝的流程，我們的方法可以在設計的早期，即考慮兩流程並同時考慮影響電壓降之相關因素，在考慮相關因素並提出兩方法之演算法後，我們產生兩種電源走線與微凸塊之位置和大小資訊，並且在結果中顯示我們可以在晶片各區塊中有效保持其電壓降小於我們設定的數值。由上述可知，過去需要經過眾多人力與時間達成電源晶片或封裝設計，藉由我們提出的自動化安排電源供應走線及微凸塊的演算法，可以在積體電路設計與封裝設計流程中，提前考慮其影響因素並進行自動化設計，且得到有效的擺放結果，得以減少在積體電路設計與封裝設計中的重複考量及修改，以縮短產品上市的時間。

關鍵字

微凸塊 ； 電源走線

並列摘要

In advanced flip-chip packaging process, power stripes and micro bumps are two key points on signal transmission and power integrity (PI) preservation to achieve vertical interconnection between substrate and chips. For different chip designs, the best arrangement strategy of micro bumps and power stripes is usually varied case by case. The procedure of design consumes lots of manpower and time cost in generating the delivery path of signal and power transmission path. To deal with this problem, two approaches are proposed to automatically generate power delivery network (PDN) on upper metal layers in a chip and set the coordinates of micro bumps. According to the chip design flow and packaging process flow, these methods can take key factors affecting the voltage drop into account and solve the IR drop problem in the early stage. After that, we generate two sets of information about the position and size of power stripes and micro bumps.
Results show that IR drop can be effectively lowered than the IR drop constraint in block. As aforementioned, the power design of chip or package took a lot of manpower and
time cost in the past. With our algorithms for automatically planning the power stripes and micro bumps, we get the effective placement results with considering the factors affecting voltage. By doing so, the iteration of consideration and modification in integrated circuit and packaging design can be decreased and thus shorten time-to-market (TTM).

並列關鍵字

Micro bump ； Power stripe

參考文獻

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