基於Starfish DSP 架構下，高效能，高彈性的模擬框架

A Fast, and Flexible Simulation Framework for Starfish DSP Architecture

唐文力(Wen-Li Tang)

指導教授 ： 鍾葉青

國立清華大學/電機資訊學院/資訊工程學系/碩士(2006年)

https://doi.org/10.6843/NTHU.2006.00376

摘要

在新型微處理器開發的過程中，模擬器是做量化評估的唯一方法。然而，對 模擬器的需求隨著開發人員的目的而有所出入。在實做開發中微處理器的模擬器 時，有許多方面是必須做取捨的。其中最重要的決策就是模擬速度，精確度和模 擬器彈性之間的考量。在這篇論文中，我們展示了經過深思熟慮的設計來達成各 個目標之間的取捨。在速度上，我們提供了一個模擬器效能的模型，創新了一個 可執行的控制流程圖(ECFG)，並展示了其中最有效的手段來加快模擬速度。在 精確度上，我們的模擬器能夠模擬時脈事件的發生，並且能夠模擬詳細的暫存器 與記憶體資訊。在彈性上，我們提供了一種分層式的方法，讓模擬器有能力可以 擴充為其他類型的應用程式。並展示如何應用分層的方式來將模擬器擴充為 GNU 除錯器(GDB)以及測試框架。除了速度和彈性的主題之外，此篇論文亦蒐 集、描述、和應用目前現有的模擬技術，來幫助模擬器架構設計師選擇最適合其 環境的模擬技術，並將適合的技術應用在Starfish DSP 模擬器之上。

關鍵字

模擬器 ； 模擬與塑型 ； 超長指令字集 ； 數位訊號處理器

並列摘要

In the development of new microprocessors, quantitative evaluation is possible
only by using simulator. However, different users have various requirements for the
simulator. The trade-off between simulation time and flexibility is the most
important decision for any simulators. This paper presents a deliberate design to
achieve those goals at the same time. For fast simulation speed, we provide a
performance model to analysis a simulator, and innovate an executable control flow
graph (ECFG). Furthermore, we also propose an effective way to improve the
performance of a simulator. For high precision, our simulator is able to simulate the
clock edge event and to expose detail register and memory information. For high
flexibility, we present a layered approach that can be extended to any kind of emulator,
even thought a GNU debugger (GDB) or a test suite. Besides the performance and
extension issues, this paper also collects, describes, applies, and compares various
simulation techniques to aid the simulator architects in selecting the most appropriate
one. We apply these techniques to the Starfish DSP simulator.

並列關鍵字

Simulator ； Simulation and Modeling ； VLIW ； DSP

參考文獻

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