雙電壓系統的標準單元擺放

在奈米技術下，由於更多的功能需求和時鐘頻率的上升，使得動態電能消耗大量增加。提供雙電壓的技術是很有效的方法防止在奈米設計下動態電流持續上升。在這篇論文中，我們採用一個用雙電壓的標準單元擺放演算法來減少總電能的消耗。另外，我們也同時減少電壓網路帶來的額外負擔。我們把已經給定好電壓的結果當作我們的輸入，然後一開始，我們用切割的工具將不同電壓的單元分成好幾個族群，第二，為了減少電能的消耗和電壓網路的複雜度，這些族群一開始將用模擬退火法演算法擺放到格子裡。第三，我們介紹一種分析式擺放演算法，將電能減少問題設成二次方程的公式。然而，這種方法會使單元之間有重疊的情況，所以我們採用單元轉移和調整單元位置的方法來解決單元重疊的問題。

關鍵字

擺放；雙電壓；標準單元

並列摘要

Dynamic power greatly increases in nanometer technologies because of increasing functional requirements as well as continuing emphasis on rising clock frequencies. The technique of supply dual voltages is one of the most effective ways to hold down the rise of dynamic power in nanometer design. In this paper, we present a standard cell placement algorithm with supporting dual supply voltages to reduce total power dissipation. Our approach also minimizes the power grid overhead by adopting voltage islands. We start at dual voltage assignment as our input. First, the cells with different supply voltages are separated into several clusters by hMETIS [6]. Second, in order to minimizing the total power consumption and power grid complexity, the clusters are first placed into a grid by using simulated annealing. Third, we introduce an analytical placement approach as a convex quadratic program formulation of the power minimization problem. However, the approach may cause overlap among cells, so we adopted the Cell Shifting and readjust cell methods [9] to reduce the overlap.

並列關鍵字

Placement ； Dual Vdd ； Standard Cell

參考文獻

[2] K.Usami and M.Horowitz, “Clustered voltage scaling technique for low power design,” In Proc ISLPED, pp. 3-8, 1995.

[3] C.Chen, A.Srivastava and M. Sarrafzadeh, “On gate level power optimization using dual-supply voltages,” IEEE Trans. On VLSI Systems, vol. 9, pp.616-629, Oct, 2001.

[4] S.H. Kulkarni, A.N. Srivastava and D. Sylvester, “A new algorithm for improved VDD assignment in Low power dual vdd systems,” In Proc. ISLPED, pp.200-205, Aug, 2004.

[5] B. Liu, Y. Cai, Q. Zhou and X. Hong, “Power driven placement with layout aware supply voltage assignment for voltage island generation in dual-vdd designs,” In Proc. ASPDAC, pp. 582-587, Jan, 2006.

[7] F. Gao and J.P Hayes, “Total power reduction in CMOS circuits via gate sizing and multiple threshold voltage,” In Proc. DAC, pp. 31-36, Jun, 2005.

國際替代計量

雙電壓系統的標準單元擺放

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