可用於超廣範圍延遲線的加速鎖定方案

Accelerated Locking Scheme for Super-Wide Range Delay Line

魏郁綺(Yu-Chi. Wei)

指導教授 ： 黃錫瑜

國立清華大學/電機資訊學院/電機工程學系所/碩士(2018年)

摘要

在現今的系統晶片、微處理器、通訊積體電路晶片以及其它時間相關的之電路設計中，延遲鎖定迴路(delay-locked loops, DLLs)及相位鎖定迴路(phase-locked loops, PLLs)已被大量且廣泛的使用於消除時間偏差。而在供應電壓越來越低的先進製程中，全數位延遲鎖定迴路(all-digital-delay-locked-loop, ADDLL) 亦有日漸取代傳統類比延遲鎖定迴路的趨勢。隨著技術不斷的發展，超寬範圍的延遲鎖定迴路也越顯重要。
在本篇論文當中，我們提出了一個全新的延遲線架構，特色是可以支援超廣延遲範圍以及快速鎖定的功能。
透過電晶體層級的模擬，我們驗證此架構可以在台積電九十奈米製程下支援10 MHz到1 GHz的單頻時脈操作。同時，與前做相較最多可以減少百分之八十八的鎖定時間。

關鍵字

延遲鎖定迴路 ； 延遲線 ； 超廣範圍

並列摘要

In today's system-on-a-chip (SOC), microprocessors, communication ICs, and other time-related circuit designs, Delay-Locked Loops (DLLs) and Phase-Locked Loops (PLLs) are widely used to eliminate the clock skew. In advanced COMS processes where supply voltages are getting lower and lower, all-digital-delay-locked-loop (ADDLL) has been increasingly replacing traditional analog DLLs. As technology continues to evolve, an ultra-wide range of DLLs will also become a trend in the future.
In this paper, we present a new delay line architecture that features an ultra-wide delay range and fast locking functionality.
With transistor-level simulation, we show that our architecture supports single-frequency clock operating from 10 MHz to 1 GHz using TSMC 90 nm process. Compared to the previous works, the lock time can be reduced by up to 88 %.

並列關鍵字

DLL ； ADDLL ； wide-range ； delay line ； Cell-based ； Long-Range

參考文獻

[1] C.-C. Chung and C.-Y. Hou, “All-digital delay-locked loop for 3-D-IC die-to-die clock synchronization,” in Proc. Int'. Symp. on VLSI Design Autom. and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 2014, pp. 1–4.

[2] Y.-H. Tu, K.-H. Cheng, H.-Y. Wei, and H.-Y. Huang, “A Low Jitter Delay-Locked-Loop Applied for DDR4”, Proc. of Design and Diagnostics of Electronic Circuits & Systems (DDECS), pp. 98-101, 2013.

[3] S.-L. Chen, M.-J. Ho, Y.-M. Sun, M.-W. Lin, and J.-C. Lai, “An All-Digital Delay-Locked Loop for High-Speed Memory Interface Applications,” Proc. VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, 2014.

[4] T. Olsson et al, “A Digitally Controlled Low-Power Clock Multiplier for Globally Asynchronous Locally Synchronous Designs,” ISCAS, May 2000.

[5] I.-C. Hwang et al, “A digitally Controlled Phase-Locked Loop with a Digital Phase-Frequency Detector for Fast Acquisition,” IEEE J. Solid-State Circuits, 36(10):1574-1581, Oct. 2001.