於0.18微米互補式金氧半製程實現之五億赫茲頻率合成器設計

Design of a 5 GHz Frequency Synthesizer in 0.18-μm CMOS Technology

汪炳義(Bing-Yi Wang)

指導教授 ： 徐永珍

國立清華大學/電機資訊學院/電子工程研究所/碩士(2010年)

摘要

頻率合成器電路在無線的通訊系中扮演了一個非常重要的角色。不論是在接收機或是發射機中都需要頻率合成器電路來產生本地的震盪頻率。而急速成長的無線區域網路市場也極力的帶動高傳輸速率與傳輸量的需求。因此，在如此困難的挑戰之下設計一個高速且低雜訊的頻率合成器電路變成是一個非常重要的趨勢。

在本論文中，我們設計即呈現了一個操作在5GHz以整數型架構的頻率合成器，並將其功率消耗做最佳化的設計。此外增加了一個類比式的迴授改善電荷幫浦中電流源不匹配的問題。振盪器電路使用的是傳統的LC震盪電路採用並聯開關的方式，降低壓控振盪器的增益以達到整體迴路低雜訊的效果。在本設計之中，振盪器的相位雜訊在1MHz的Offset頻率達到了-112dBc/Hz的效能，換算成FOM指數約為185。在除頻器的設計中，我們採用電流式邏輯為基底的電路，他可以使得除頻器電路達到寬頻的除頻效果。根據Post-Layout 的模擬結果，前四級除頻器的輸入頻率讓其可正確可除範圍約為1.2 ~ 7.3 GHz。如此寬頻的設計使得它可以避免製程與溫度的變異。

最後，本研究採用的是TSMC 0.18mm 1P6M RF製程來實現頻率和成電路晶片，整體的電路的面積約為1.2 x 1.3mm2。

關鍵字

鎖像迴路 ； 頻率合成器

並列摘要

A Frequency Synthesizer plays an important role in wireless communication systems. Both transmitter and receiver need the synthesizer to generate local oscillation frequency. The growing wireless LNA market has generated increasing interest in technologies that enable higher data rates and capacity compared to those of previous implementation. Hence, design a low power frequency synthesizer with good noise performance is a significant work.
In this work, a phase locked loops based integer-N frequency synthesizer with optimal power consumption is presented. This PLL employs an analog feedback charge pump circuit for low noise application. The oscillator is implemented by conventional LC-tank, with switch capacitance to achieve low spur and low phase noise. At 5.12GHz, the VCO system demonstrates a phase noise of -113dBc/Hz at 1MHz offset with dissipation 1.5mA at a 1.2-V supply. This corresponds to a FOM of 188dBc/Hz/mW. For the divider chain of this work, current-mode logic based frequency dividers are adopted in four-stage cascaded-dividers after LC based buffer. This will allow the system to generate a wide-locking-range characteristic. According to the post-layout simulation of the CML divider chain, they achieve a 1.2 to 7.3GHz locking range wide. This result shows that the divider chain implemented can correctly operate under possible PVT variations.
Finally, this frequency synthesizer has been fabricated in a TSMC 0.18 um 1P6M RF/Mixed-Mode Process. The whole circuits occupy an area of 1.2 x 1.3mm2.

並列關鍵字

PLL ； Frequency Synthesizer

參考文獻

[1] C. F. Liang, S. H. Chen, and S.I. Liu, “A Digital Calibration Technique for Charge Pumps in Phase-Locked, Systems,” IEEE J. Solid-State Circuits, vol. 43, no. 2 , Feb. 2008.

[2] S. Pellerano, S. Levantino, C. Samori, and A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-Logic frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 2, pp. 378–383, Feb. 2004.

[3] H. R. Rategh, H. Samavati, and T. H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, May. 2000.

[4] C.M. Hung, and Kenneth K.O. “A fully Integrated 1.5V 5.5GHz CMOS Phase-Locked Loop,” IEEE J. Solid-State Circuits, vol. 37, no. 4, Apr. 2002.

[6] C.T. Charles and D. J. Allstot. “A Calibrated phase/frequency detector for reference spur reduction in charge pump PLLs,” IEEE Trans. Circuits Syst. II, Exp. Brief. vol. 53 pp822-826, Sep, 2006.