表面電荷效應和非晶化結構在多晶矽閘極和超淺接面之電性研究

THE CHARACTERIZATIONS OF SURFACE CHARGING AND PREAMORPHIZATION IN POLYSILICON GATE AND ULTRA SHALLOW JUNCTION FORMATION

陳律璋(Lu-Chang Chen)

指導教授 ： 吳孟奇

國立清華大學/電機資訊學院/電子工程研究所/博士(2011年)

摘要

隨著半導體製程技術的推進,所需使用的離子種類、植入劑量和能量跟著有所改變,而所衍生出來的電性差異現象也會隨著製程技術朝向奈米尺寸微縮,而在小尺寸的半導體元件上有所不同。本論文中,我們探討硼離子以低能量植入條件下,對於表面電荷累積所造成元件電性和薄氧化層上的影響,以及植入離子束的電流密度在不同種類的離子植入下,晶圓表面溫度的變化程度在光阻層和多晶矽閘極上所產生的熱效應和表面電荷的缺陷影響。實驗結果顯示,在完全沒有或不足夠負電荷中和表面正電荷的條件下,從元件電性量測結果上,在表面正電荷累積的樣本會產生較高的阻值、較低的氧化層崩潰電壓以及增益。另一方面,在不同種類的離子以及電流密度下,質量數較重的離子,例如砷離子,佈植在多晶矽層會在表面產生比質量數較輕的離子,例如硼離子,會因為能量轉移而產生較高的表面溫度。而所產生的表面熱效應會使得光阻層和多晶矽層表面遭受破壞以及形成正電荷累積,以至於影響後續植入的離子表現,因此使得實際植入的離子劑量及深度表現有所差異,形成較高的多晶矽層阻值。在本論文中,我們對於不同比例的鍺同位素離子佈植在製程上的影響亦有所探討,利用鍺離子佈植技術來形成預先非晶化結構是製作超淺接面的技術之一。不同比例的鍺同位素離子佈植會產生不同程度的非晶化層厚度,使得後續佈植的硼離子在高溫熱處理後有不同的深度表現。因為離子佈植所產生的缺陷密度跟位置,會形成不同的硼離子擴散深度而有短通道效應影響,以至於在元件電性上產生不同的差異結果。從電性量測結果,我們可以得到一個結論,對於質量數為74 且成分比例愈高的鍺同位素離子,會形成比較薄的非晶化層厚度跟較多的缺陷密度,在接續植入的硼離子會有明顯的擴散現象,形成較深的接面深度使得短通道效應比較明顯,在元件電性上會產生束限電壓及效益退化和比較差的漏電流。然而質量數為72的鍺同位素離子,會有比較好的抑制硼離子擴散效應的能力,減少短通道效應而有較佳的元件電性表現。

關鍵字

表面電荷效應 ； 非晶化 ； 短通道效應

並列摘要

As the gate length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is of the order of nanometers, it is very difficult to maintain their electrical properties with the different species, accelerated energy and implant dosage. In this thesis, we study the effects of surface-charge on MOSFETs devices by a positive ion-implanted beam accompanying an electron-beam current for surface-charge neutralization. Without or insufficient for the negative electron-beam current, films show a higher sheet resistance, a lower threshold voltage, breakdown voltage, and gain factor. If the electron-beam current is equal to or higher than the ion-beam current, the uniformity of sheet-resistance and the fluctuations of breakdown voltage and gain factor will be significantly improved by controlling the charge neutralization. It will prevent the positive ion charges from penetrating through the poly-gate to cause the catastrophic damages in the gate-oxide layer.The effects of arsenic-ion implanted beam density on defect evolution in photoresist and polysilicon film also have been investigated. The ion implantation by heavy ions, such as arsenic ions, would induce an elevated temperature and positive charge accumulation on the photoresist film and polysilicon surface at a high implanted beam density, due to the accelerated energy transfer into the implanted amorphous area. The popping generation upon the photoresist film at a higher surface elevated temperature and the polysilicon resistance linearly increases with the implanted-ion beam density after a subsequent annealing process. Therefore, by optimizing the ion beam density, the surface temperature and charge accumulated potential would be reduced and well-controlled to obtain a stable polysilicon sheet resistance at the role of gate electrode.In this thesis, we also study the influence in the nano-scale gate length of pMOSFETs technology using germanium preamorphization implantation (Ge PAI). It is demonstrated that the channeling can be eliminated and minimize the short channel effect by the formation of a Ge-implantation induced thin amorphous layer near the surface prior to boron implantation. Optimizing the amorphous layer thickness by controlling a high 72Ge/74Ge ratio, the device performance of pMOSFETs can be enhanced. It is also found that the thin Ge PAI amorphous layer formed by a low 72Ge/74Ge ratio would cause the degradation of threshold voltage (Vth) roll-off characteristics and Ion/Ioff ratio, as compared to that formed by a high 72Ge/74Ge ratio. It is attributed to a thinner Ge amorphous layer that has a weak ability to suppress the tail of boron ions, as compared to a thicker Ge amorphous layer at the same implanted doses and energies among various 72Ge/74Ge ratios.

並列關鍵字

surface charging effect ； preamorphization ； short channel effect

參考文獻

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