高階合成階段之最小化矽穿孔數量的後處理方法

A Post-Processing Approach to Minimize TSV Number in High-Level Synthesis

黃琮淯(Tsorng-Yu Huang)

指導教授 ： 黃世旭

中原大學/工學院/電子工程研究所/碩士(2010年)

https://doi.org/10.6840/cycu201000712

摘要

三維積體電路(Three Dimensional Integration Circuits, 3D IC)技術乃是將多種晶片立體堆疊化的整合模式，且三維積體電路的應用也越來越普遍，因此開發電子設計自動化（Electronic Design Automation,EDA）工具來因應積體電路由傳統的兩維結構轉換為三維結構也相對變得迫切和重要，在本篇論文中，我們提出一套整數線性規劃(Integer Linear Programming)，用於高階合成階段時執行資源層分配(Resource Layer Assignment)的工作，我們主要的目標是在有晶片堆疊層數和晶片涵蓋面積的限制條件下最小化矽穿孔(Through Silicon Via, TSV)的數量。
我們的方法能有兩種應用：(1)三維積體電路於高階合成階段時以後處理方法來執行矽穿孔數量的最小化；(2)以後處理方法將電路設計由兩維積體電路結構轉換為三維積體電路結構。
而值得一提的是，我們的方法能夠保證將矽穿孔的數目降至最低，實驗結果顯示，我們的方法在實際的測試例子中仍然能夠有效的降低矽穿孔數量。

關鍵字

高階合成 ； 電子設計自動化 ； 整數線性規劃 ； 三維積體電路。 ； 資源層分配

並列摘要

Three Dimensional (3D) IC technology stacks multiple integrated chips and its application is more and more popular. Therefore, developing EDA tools for the requirement of 3D architecture becomes urgent and important. In this thesis, we present an integer linear programming (ILP) model for the application of resource layer assignment in high level synthesis. Our objective is to minimize the number of signal through-silicon-vias (TSVs) under both the layer number constraint and the footprint area constraint.
Our work includes two possible applications: (1) a post-processing method to perform TSV number minimization for high-level synthesis of 3D ICs; (2) a post-processing method to transfer a design from 2D IC structure into 3D IC structure.
Note that our approach guarantees minimizing the number of TSVs. Experimental data consistently show that our approach works well in practice.

並列關鍵字

Electronic Design Automation ； Resource Layer Assignment ； Integer Linear Programming ； High-Level Synthesis ； Three Dimensional Integration Circuits.

參考文獻

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